Aurix safety processor gets AI accelerator
AI and neural networks are essential building blocks for automated driving, for example in the classification and tracking of objects or in determining the route in traffic. In addition, they help to optimize many other automotive applications, reduce the cost of ECUs, improve their performance and accelerate their market launch. For example, AI and neural networks enable optimized autocalibration of engines and reduce the number of sensors required by generating precise mathematical models of the physical reactions in a system. At the same time, AI applications require significantly more computing power than standard algorithms. Therefore, Infineon’s Aurix microcontrollers will be equipped with a Parallel Processing Unit (PPU) specifically for processing AI algorithms. For the development of the PPU, the chip manufacturer uses the processor IP of the ARC EV from Sysnopsys.
The PPU is intended to ensure that the Aurix microcontrollers meet the increasing requirements for computing power in terms of security, data throughput and energy efficiency,” says Peter Schäfer, head of the microcontroller business in Infineon’s Automotive Division. The measure is intended to make the Aurix fit for data-intensive automotive applications such as future gateways, domain and zone controllers, engine control, electromobility and advanced driver assistance systems.
The PPU will take the real-time and AI capabilities of the Aurixes to a new level. The performance of the PPU will be significantly higher than the current accelerators, promises Infineon. This will enable the microcontrollers to process data from sophisticated sensors, for example, which is currently not possible due to the high real-time requirements. The PPU will accelerate KI algorithms such as RNN (Recurrent Neural Network), MLP (Multi-Layer Perceptron), CNN (Convolutional Neural Network) and RBF (Radial Basis Function).
By supporting CNN, the PPU will also facilitate the development of holistic security systems in addition to safety. It will enable multi-layered security concepts that support techniques for Intrusion Detection and Prevention (IDP) systems, such as Deep Packet Inspections or System Entropy Monitoring.
Related articles:
Synopsys: Functional safety and high uptime in FPGAs using TMR
Synopsys rolls ASIL-certified processor IP to ADAS designers
“Security has to be mandatory for automotive software development”
Synopsys grows ASIL-ready ISO 26262-certified IP function offering
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
