Austriamicrosystems releases new versions process design kit for 0.18-um high-voltage CMOS technology
Based on Cadence Virtuoso custom design platform (both, IC 5.1.41 and 6.1.4 releases), the new HIT-Kits significantly improve the time-to-market for highly competitive products in the analog intensive mixed signal, smart sensor and System-on-Chip arena. Supporting designers in creating their first-time-right mixed signal designs even for complex designs, this comprehensive design environment with its highly accurate simulation models and flexible SKILL-based PCells provides a proven route to silicon.
Both new HIT-Kits, version 3.78 (qualified for IC 5.1.41) as well as version 4.01 (qualified for IC 6.1.4) support the 0.18 µm specialty process technology H18 (High-Voltage CMOS) which is based on IBM’s industry proven foundry process technology CMOS7RF. The kits come complete with silicon-qualified digital, analog and RF library elements, complete sets of low voltage devices (1.8 V and 5.0 V) and high-voltage devices with various gate oxide thicknesses (20 V and 50 V devices).
Fully characterized simulation models, extraction and verification run sets for both, Calibre and Assura and automatic layout device generators (pcells) are included. Routines such as Safe Operating Area verification tool (SOAC) as well as a Life-Time simulation tool complete the H18 HIT-Kit offering; hence product developers are enabled with a plug-and-play tool set which facilitates "first time right" designs.
The digital standard cell libraries included in this H18 HIT-Kit have a gate density of 118 kGates/mm² and are available both in standard and low leakage versions. Furthermore all I/O structures within the design kit are silicon-validated and meet the military ESD and JEDEC latch-up standards with I/O pads designed to surpass 4 kV HBM and 250 mA latch-up immunity.
More information about the new HIT-Kit version at
https://asic.austriamicrosystems.com/hitkit378 and https://asic.austriamicrosystems.com/hitkit401.