Automating PCB trace selection in signal integrity simulation
Antmicro has developed an open source automated workflow for selecting key PCB traces for board simulation tools.
Antmicro offers end-to-end hardware design services based on open source toolkits and workflows, including interactive system diagrams, automatically generated 3D renders and a vast component database, for an iterative and software-driven design process. To ensure automated and comprehensive testing for complex, multi-layer PCB designs before manufacturing, the workflow includes not only signal integrity analysis with S-parameter, impedance, Smith etc. charts and eye diagrams, but also electromagnetic field scanning which is crucial for size-constrained devices.
Many of its projects focus on complex applications such as video processing or high-speed connectivity with impedance-controlled nets that must be designed following strict criteria to ensure signal integrity. This is especially important to the performance of high-speed digital interfaces, such as MIPI CSI-2, DDR or PCIe.
Antmicro created a tool called gerber2ems that converts PCB production files generated with tools such as KiCad into PNGs which can then in turn be further processed and used for simulation with openEMS. Signal integrity simulation provides invaluable aid in prototyping complex designs, such as DDR5 memories, high speed FPGAs and SoCs, quicker and more reliably.
Signal integrity simulation flow
To prepare input data for simulations, the critical traces to be simulated need to be selected. Due to the complexity of the simulation process, each trace or differential pair needs to be considered separately. Simulation ports need to be placed at the beginning and the end of the simulated trace and other copper fields need to be reduced, cleaned and terminated (assigned an impedance at the ends). Previously this was performed manually, but the automation developed by Antmicro produces a set of scripts for generating the simulation cases and organizing the output.
The current flow for performing signal integrity simulation, visualized in the diagram below, consists of the following steps:
- Selecting signal nets to be simulated
- Creating simulation cases – PCB slices and simulation configuration files
- Manual data adjustment – user can alter the simulation setting or port placement
- Exporting PCB slices to a 3D mesh of conductive/dielectric primitives with gerber2ems
- Simulation with OpenEMS
- Generating visualizations of the simulation results
- Presenting the board simulation summary on Open Hardware Portal
The open source hardware boards are designed in KiCad which provides great flexibility including custom scripts and plugins. The KiCad Pcbnew Python API provides PCB modification capabilities with Python scripting and Antmicro used this to create a Python package that prepares input data for its signal integrity analysis workflow.
si-wrapper slice creates simulation cases – board slices of the analyzed PCB, which are the main input to the gerber2ems script. As the slice covers a particular net, its minimal size is determined by the span of the net. The script’s config defines the size of a margin added to the minimal dimension, and criteria of inclusion of neighboring nets – parts of signal traces next to the analyzed net/pair, which can influence signal propagation and should be included in the simulation.
A slice prepared for simulation contains the designated net (or a pair of nets in case of a differential pair), neighbouring nets and all vias and planes present in the area. Passive elements like 0 Ω resistors and significantly large capacitors are replaced with a short – a trace connecting pads of their footprints. This approximation is valid for the frequencies of interest and avoids the limitations of the OpenEMS simulator. The neighbouring nets are terminated with their nominal impedance. In case of power nets and low speed interfaces, a 0 Ω termination is assumed.
The final operation in preparing the PCB slice is the placement of the Simulation Ports on the analyzed net, as well as the neighbouring nets.
A Simulation Port represents a signal source and sink in the simulation. A single net simulation requires two Simulation Ports, while a differential pair should be marked with four. The neighbouring nets also require placement of the Simulation Ports, representing their termination impedance.
The si-wrapper slice script automatically determines the correct positions of the ports and pinpoints them with markers, implemented as a virtual Kicad footprint. The ports are placed at the beginning and the end of a particular net. The script searches for Kicad components connected to the net, and marks the end of the net’s trace section closest to the center of the terminating component pad. The port orientation is determined based on the pad orientation. The simulation software limits the port orientation to one of the four major directions on the plane. Every Simulation Port has an assigned number which can be also found inside simulation configuration.
If the si-wrapper slice script fails to identify the correct number of ports – which can happen, for example, if the trace fails to follow the two-point configuration, which is recommended for a high-speed routing – it prompts the user to adjust the port placement. This can be achieved by editing the PCB slice with Kicad, and running si-wrapper renumerate.
SO-DIMM DDR5 Simulation configuration
The simulation configuration file and net information file are generated along with the slice. The simulation configuration file contains all crucial simulation parameters that can be adjusted, but the default settings work in the majority of cases. The configurable parameters are described in the gerber2ems README. The net information file consists of the designated net name, width, length, impedance, single/differential net flag, and temporary links to the results.
A simulation of an open hardware SO-DIMM (LP)DDR5 tester features a DDR5 interface (or, in an alternative configuration, LPDDR5), which, due to high clock speeds, is particularly sensitive to signal integrity issues. Simulation of the memory interface’s clock, address and data traces provides a valuable tool for verification and quality assurance of the design.
This generated simulation cases for the whole PCB by picking nets from the “controlled impedance” class defined in the Kicad project. The selection is performed by the si-wrapper settings script and the selected nets are processed with si-wrapper slice to produce the simulation cases.
Antmicro has created a broad portfolio of open source hardware designs in its Open Hardware Portal.
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