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Automotive SoC featuring Tensilica AI IP demonstrated

Automotive SoC featuring Tensilica AI IP demonstrated

Technology News |
By Jean-Pierre Joosting



Cadence and Dream Chip have showcased the latest automotive SoC from Dream Chip, which features the Cadence® Tensilica® Vision P6 DSP IP and Cadence design IP controllers and was taped out using the complete Cadence® Verification solution and full-flow digital implementation, including signoff.

The advanced driver-assistance system (ADAS) application software, operating on the Tensilica AI IP within the Dream Chip SoC development board, was a highlight of the demonstration at Embedded World 2024 earlier this year.

This innovative SoC utilizes the GlobalFoundries  22FDX® technology platform, which is ready and proven for energy-efficient automotive customers. The SoC was designed in a publicly funded project, ZuSE-KI-Mobil (ZuKIMo). ZuKIMo focuses on developing an AI accelerator system on chip (SoC) for advanced driver assistance systems (ADAS). Manufactured in Dresden, Germany, the SoC supports the local European semiconductor supply chain for automotive applications.

The Cadence Verification, Implementation and Signoff products enable automotive designers to quickly deliver first-time silicon success while achieving safety, quality and reliability goals, enabling certification up to ISO 26262 ASIL-D, with minimal impact on system power, performance and area (PPA) targets. This cutting-edge SoC leverages the capabilities of Cadence verification and RTL-to-GDS digital full-flow offerings, meticulously fine-tuned to meet the stringent safety, quality and reliability standards required in the automotive industry.

It also leverages the optimal ADAS features with the industry-leading Tensilica Vision P6 DSP and AI cores by incorporating Tensilica AI processors and a sophisticated array of Digital IP controllers. These include Cadence’s pioneering NPU AI IP, multi-functional Ethernet 10/100/1G MAC, essential control features such as SPI and RTC Control, and SD 6.0/eMMC 5.1 Host Controller and PHY. This strategic integration of hardware is designed to power energy-efficient ADAS applications that utilize evolving technologies like lidar, radar and vision-based systems at the edge, significantly enhancing the automotive-grade quality, safety and reliability of autonomous, connected and electrified (ACE) vehicles.

Commenting on the milestone, Dr. Jens Benndorf, managing director and CEO of Dream Chip Technologies, said, “We collaborated closely with Cadence to provide a full automotive solution highlighting Cadence Tensilica AI-at-the-edge performance along with functional safety and the latest image signal processing to automotive OEMs and Tier-1s. Dream Chip fully implemented and signed-off the energy-efficient automotive SoC from architecture spec to running software using Cadence Verification along with the Cadence Digital EDA full-flow on the GlobalFoundries 22FDX process, showing that Dream Chip is an optimal design house choice for advanced automotive SoCs.”

David Glasco, VP of research and development, Compute Solutions Group at Cadence, added, “The choice of Tensilica IP by the ZuKIMo coalition along with Cadence’s focus on design innovation and excellence across all aspects of the safety-critical and high-reliability IP and the design and verification flow has resulted in this powerful ADAS demo.”

The demonstration highlighted the advanced SoC capabilities, demonstrating the power and flexibility of Cadence’s Tensilica IP in driving optimal ADAS features with the industry-leading Vision and AI cores.

www.cadence.com

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