AWGs offer up to 24 synchronous channels

AWGs offer up to 24 synchronous channels

New Products |
By Graham Prophet

Applications such as MIMO, radar, quantum computing and multi-lane serial bus testing, and others with multi-receiver/emitter or multi-sensor technology, gain from the ability to generate multiple synchronized test or stimulus waveforms. Fast Arbitrary Waveform Generators (AWGs) have become the instruments of choice as they allow easy and flexible signal generation. However, most high-performance AWGs only provide a limited channel count (1 to 4), which can make creating larger test systems quite expensive. In addition, these AWGs face serious problems when systems are scaled up for higher channel count applications as they typically present synchronization issues.


The DN6.66xx series adds eight new instruments to the company’s generatorNETBOX line of AWGs. LXI compliant, they can be integrated into any test system by an Ethernet connection to a PC or local area network (LAN). Using 16 bit DACs, the AWGs offer from 6 to 24 fully synchronous channels, output rates up to 1.25 Gsample/sec, analogue bandwidth up to 400 MHz, large on-board memories (up to 1 GSample per channel) and output voltage ranges of up to ±5 V into high impedance and up to ±2.5 V into 50Ω.


Alll the output channels are clocked and triggered synchronously so they maintain a constant, inter-channel clock phase relationship. The clocking system uses a precision phase locked loop (PLL) control process that can be generated internally or, alternatively, from an external clock or reference. Time skew between the channels is also minimized with the maximum skew, between all channels, being less than 130 picoseconds.


To allow the generation of long and complex waveforms, the AWGs combine their large on-board memories with a number of operating modes such as Single-Shot, Loop, FIFO, Gating and Sequence Replay. Sequence Mode cuts the memory into segments of different length and combines them with a sequence of commands including loops for more efficient memory use.


For further system flexibility, front-panel multi-purpose I/O connectors provide access to multiple marker outputs, asynchronous digital inputs, asynchronous digital outputs, the trigger output, the run and arm status and the PLL reference clock. Signal generation software is included.





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