Dutch AI chip startup Axelera has detailed its analogue in-memory computing for machine learning applications.
In a paper at the ISSCC conference in the US this week, the company has detailed its DIgital and ANAlog (DIANA) hybrid neural network architecture that supports a variety of disparate, mixed-precision machine learning workloads on-chip.
The chip combines a 4 to 8bit digital neural network accelerator and RISC-V host processor with a shared memory subsystem to a 1152 x 512 analog in memory computing (AiMC) core.
The shared memory subsystem allows simultaneous execution of neural layers across the digital and analog cores, running the high precision layers on the digital accelerator and the intermediate layers on the AiMC core. This is a 64way single instruction, multiple data (SIMD) six-stage pipelined architecture. This produces 64 outputs in parallel for the common neural network operations.
This is a revision of the AnIA analog-in-memory compute matrix-vector-multiplication unit designed by chip architect Stefan Cosemans and senior mixed-signal designers Ioannis Papistas and Bram Rooseleer during their time at Belgian research centre imec.
The first chip to use DIANA is built on a 22FDX 22nm FD SOI process from Globalfoundries and measures 8.91mm2, with 2.2mm2 for the analog macro with the SRAM and data converters where the in-memory computing occurs. Using the digital core the chip achieves 4.1TOPS/W. Using only the AiMC core the chips achieves 410TOPS/W with the core itself achieving 600TOPS/W, showing the impact of the data conversion.
On a real workload, such as the ResNet-20 network, the digital element achieved 2.1TOPS/W at 0.55V, while the hybrid combination achieved 14.4TOPS/W.
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