Back to vacuum tubes: at the nanoscale

Back to vacuum tubes: at the nanoscale

Technology News |
By Julien Happich

Describing their “Nanoscale Vacuum Channel Transistor” or NVCT in the Nano Letters journal, the researchers come back to the fundamentals: vacuum provides superior electron transport compared to all semiconductors (no collisions or scattering in the absence of crystal lattices).

Reviving the defunct vacuum tube, the researchers leveraged modern silicon nanofabrication technology to create a novel type of transistor sporting a vacuum channel instead of a doped semiconductor. Learning from the evolution of planar CMOS FETs to FinFETs and more recently gate-all-around FETs, the team from NASA opted for a surround gate design for optimal local field enhancement.

Their vacuum channel transistor consists of sharp source and drain electrodes separated by a nanoscale vacuum channel (less than 50nm apart), and a surrounding gate delimiting the cylindrical vacuum channel (with a channel radius of 10nm, equivalent to the source-to-gate distance).

Although the device is not “sealed” and the channel is technically an air-channel, because the 50nm channel distance is smaller than the mean-free-path of air molecules under atmospheric pressure, it can be considered as quasi-vacuum, the researchers explain.

Schematic illustrations of (a) a silicon nanowire gate-all-around transistor and (b) a nanoscale vacuum channel transistor. A comparison of the energy band diagrams in the source to channel direction, xz-plane, of the (c) silicon nanowire gate-all-around transistor and (d) the nanoscale vacuum channel transistor.

The paper draws similarities between the NVCT structure and that of a nanowire gate-all-around transistor, except that the silicon channel is replaced by an empty gap and the source is sharpened for local field enhancement. Both share analogous operation mechanisms, the researchers write.

The NVCTs were fabricated on 8-inch wafers using top-down silicon technology with no exotic materials at a standard 0.18μm fabrication facility. Lithographic limit was overcome by photoresist trimming and a local sacrificial oxidation process. The result were NVCTs with a turn-on gate voltage of 2V and yielding a drain current of 3μA for a gate voltage of 5V.

“Though the gate voltage is efficient to extract the source electrons, the drain terminal collects the most current rather than the gate intercepting the current since the gate dielectric blocks such leakage. The gate leakage current is just of the order of pA, 106 times smaller than the drain current”, the paper reads.

Contrarily to semiconductor chips which bear an intrinsic risk of failure due to a number of ionizing factors (exposure to high temperature and radiation environments), the NVCTs were proven to be highly immune to such conditions (no scattering in the vacuum channel hence no formation of electron−hole pairs also known as ionization events).

“At 200°C, where the silicon based CMOS most likely loses its function, the NVCT shows nearly identical I−V characteristics at room and high temperatures” the paper reports.

To top it up, the researchers exposed their design to γ radiation at total dose levels of 1, 10, and 100KRad, observing no change in the turn-on voltage and the drain current. The NVCTs were also bombarded with protons at doses of 0.1, 0.3, 0.5, 1, and 5Mrad and again, which didn’t impact noticeably the turn-on voltage and the drain current.

The authors expect such nanoscale vacuum transistors to become an integral part of electronics beyond the Moore’s law era, more particularly for high frequency devices, THz electronics, radiation tolerant space electronic circuits, and deep space communications.


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