Backside of the wafer promises 3D chip improvements
IMEC fellow Eric Beyne, 3D program director, and Julien Ryckaert, program director of 3D hybrid scaling, laid on the numerous options that are either already pursued commercially, or could be soon, in a meeting with press ahead of the IMEC Tecnology Forum.
With the increased difficulty of planar miniaturization integration in 3D has been pushing its way on to the agenda for a number of years. However, a lack of support for 3D design from EDA companies has somewhat hampered adoption. In addition, such developments as CoWoS [chip-on-wafer-on-substrate] and InFO [Integrated Fan-Out] packaging offered by TSMC while offering high-performance integration have only appealed to a few customers.
As a result the volume of manufacturing that would drive EDA companies and packaging companies to support the technology has been hard to achieve.
However, the exponentially increasing cost of planar integration is compelling the search for alternatives. This is one of the things that is driving the increasing adoption of 2.5D integration for logic and memory (see TSMC preps for ‘chiplet’ style manufacturing in 2021).
Beyne portrayed a spectrum of 3D integration opportunities that spans eight orders of magnitude for circuit interconnect pitch density from the millimeter scale to the nanometer scale.
The 3D interconnect technology landscape. Source: IMEC
The highest-level technique is the stacking of packaged components. Next is the use of multiple die in a single package using a passive interposer, this is known as 2.5D integration. Next is die-stacking using microbumps, which is at about the same level of interconnect density as wafer-to-wafer bonding prior to dicing. Beyond this we enter the realms of in-fab processes such as wafer-to-wafer sequential processing and transistor stacking.
Some transistor stacking has been attempted in the commercial world with 3D NAND memory with up to 96 layers being the most obvious, but a specialized, example (see Samsung ramps production of 96-layer 3D-NAND flash).
Next; Beyne and Ryckaert go further
Beyne and Ryckaert laid out a few of the ideas that are starting to look promising at IMEC at the more aggressive end of that spectrum.
One is functional partitioning and wafer-to-wafer bonding. This would allow memory to be manufactured in a memory-optimized process on one wafer and core logic to be manufactured on another with a potential reduction in die area and an obvious reduction in footprint. It also allows functional memory to be positioned in close proximity to the logic it serves, resulting in increased performance at reduced power consumption. However, to achieve these benefits does require support from EDA firms.
A second refinement proposed by IMEC is the used of backside power delivery networks (BPN). Conventionally all signal and power interconnect is done through back-end-of-line (BEOL) processing on the front-side of the wafer.
This would require thinning of wafers to about 500nm to expose nanometer-scale through silicon vias (nTSVs). Moving BEOL power distribution to the silicon backside allows direct delivery to the standard cells, would enhance system performance, increase chip area utilization and reduce BEOL complexity, Beyne said.
Different forms of 3D that may evolve from standard frontside processing. Source: IMEC.
BEOL = back end of line; PDN = power distribution network; uTSV = micro through silicon via; BPR = buried power rail; W2W = wafer-to-wafer
“We are working with EDA companies on full sign-off [of 3D integrated circuits]. There is a good path there,” said Beyne. He added that the reliability of nanoTSVs with dimensions of 250nm by 180nm and depth of 500nm is approaching that of conventional BEOL.
Next Ryckaert picks up
Ryckaert picked up the story from the IC manufacturing point of view. “We will probably run out of room to pack devices closer together. So we need to go higher to gain density,” he said.
While sequential 3D processing to lay down multiple layers of circuits is possible there are often concerns about high temperature processes and their impact on previously characterized layers. In addition power delivery on very complex 2D circuits requires very fat lines to distribute power to core logic and SRAM.
Making use of the backside shows great appeal, he said. “Maintaining SRAM performance will be very challenging down to iN5 [IMEC 5nm node],” he added indicating that the benefits of less metal layers, less congestion and improved IR drop could help maintain SRAM performance.
This functional backside technology is under development at IMEC as part of the 3D program and electrical results are on target. IMEC has demonstrated the use of microTSVs
Ryckaert added that functional backside processing can be seen as a pseudo sequential 3D processing but that offers double-sided BEOL. Although separating signal and power has a simple appeal functional backside processing could also be used for other things such as clock and internal bus distribution; the addition of MiM capacitors, IGZO devices and non-volatile memory and I/O.
When asked if MRAM could be a replacement for SRAM in such 3D assembly schemes, Ryckaert said: “We believe in non-volatile memory. SRAM could be replaced with something although MRAM would tend to go in the BEOL. But just using the backside for MiM capacitors could produce a tremendous improvement.
Related links and articles:
News articles:
TSMC preps for ‘chiplet’ style manufacturing in 2021
EDA tools support TSMC InFO 3D packaging
Samsung ramps production of 96-layer 3D-NAND flash
Toshiba starts sampling 96-layer, quad bit 3D-NAND
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