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Backside power is key to 1nm scaling says Intel

Backside power is key to 1nm scaling says Intel

Technology News |
By Nick Flaherty



Intel is demonstrating key technology for scaling transistors at 1nm and beyond using backside power contacts at the IEDM conference in the US today.

Intle has already shown backside power vias, connecting power rails from the back of a wafer which will be implemented in the Intel 18A 1.8nm process technologies. Backside power contacts will enable scaling to 1nm and beyond. 

“We are very excited to be the first to implement backside power vias in 18A,” said Paul Fisher, Director of Chip Mesoscale Process Development at the Components Research.

This is a key part of the next step for stacked ribbon transistors.

“At IEDM we will be providing a comprehensive description beyond power vias,” said Mauro Kobrinsky Intel Fellow and technology development director.

“Before backside power delivery processors a built in layers with multiple layers of metallic wires. Moore’s Law drives more transistor and this drives more layers and smaller wires which increases the complexity and the cost. Each layer has to provide wires for signalling and power and this typically leads to optimisation compromises and competition for resources, the interconnect bottleneck and this has been more and more challenging.”

“Backside power fundamentally changes the situation for the better with interconnects on both sides of the device and vertical interconnects, the power via proper. We are able to deploy this technology next year in 20A and 18A and this means less wires on the front side so we can relax the pitch and no longer need to make optimisation compromises,” he said.

“Beyond power via our research is on backside contacts which allow us to connect transistors from both sides of the device for the first time. We have been able to fabricate these contacts in our research vehicles and that the front and backside contacts are matched without having to route with power vias. This allows us to decrease the capacitance of the cells for higher performance at lower power,” he said.

Intel has used this interconnect for integrated transistor stacking with NMOS devices on top of PMOS in a ribbon to build an inverter gate.

“This creates an interesting challenge with power and signalling at the same time, with backside contacts and power vias. A meaningful stacking process requires the ability to stack devices but also to interconnect them in an area efficient manner. If the interconnect increases the footprint we lose the effect of the transistor density we are trying to achieve so this has to have low footprint and backside contacts and power vias and the stacked gate connections are key for this,” he said.

The lower transistor in the stack connects to the back of the wafer and the top transistor to the top, while via connect through the stack. This avoids the need for more contacts on the top of the stack.

A key step is that Intel confirmed that using backside contacts does not impact the thermal behaviour so there are standard thermal improvements with scaling over time.

“This allows us for the first time to align features on the front side and the backside of the wafer and we have identified multiple paths for frontside to backside alignment. We have made significant improvements in achieving this overlay. This is essential for a practical device stacking implementation,” he said.

The stacked CFET complementary devices have been built in a process that scales.

“There is a great synergy between our transistor scaling and interconnect work as we want to maximise our density improvements,” said Marko Radosavljevic, principal engineer at Intel.

“Without backside contacts we would need additional topsides contacts which increases the footprint. We have combined backside contacts with device stacking at a much more scaled research vehicle, with a poly pitch of 60nm which is quite scaled compared to the work we showed on 2021,” he said.

Intel has used the stacked transistors for an inverter gate on a single fin

“We have three ribbons, three each for nmos and pmos, and we have to figure out how to create the pn junctions,” said Radosavljevic. “This is a novel technology, where we need to extend to a vertical patterning technology to operate on the top part of the stack or the bottom and separately we need connections. We use the power via to connect the top device to the back of the wafer and a backside power contact to connect the bottom device. We connect the gates together using the gate control.”

“An inverter requires the sources of the transistors to be connected and we use a wraparound contact from the topside that connects the top device to the bottom device in an area efficient way rather than going around the device and we are demonstrating all of this together in silicon.”

“An inverter is the simplest circuit we can create, and this is created in the same transistor with device stacking combined with the power via and backside contact. We are very excited about the prospects of this research as this is a significant improvement in device density going forward,” he said.

www.intel.com

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