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Backside power key to Intel process

Technology News |
By Nick Flaherty


Intel’s process technology plans have highlighted the role of backside power technology. 

This provdes power from the back of the wafer, avoiding the need to route large power lines over the top of a chip and enabling a smaller die. This has been pioneered by imec in Belgium.

Backside power articles on eeNews Power 

The key change is the A-series process nodes from 2023. The 20A process will be the equivalent of 2nm, starting in the middle of 2024, and will use two breakthrough technologies, RibbonFET and PowerVia.

PowerVia is Intel’s version of the backside power delivery, optimizing signal transmission by eliminating the need for power routing on the front side of the wafer and so reducing the die size and cost of devices. Intel 20A is expected to ramp in 2024 and the company is working with rival Qualcomm on how to use this process technology a part of Intel’s foundry offering.

RibbonFET is Intel’s implementation of a gate-all-around transistor that Samsung is already using for its 3nm production. This will be the company’s first new transistor architecture since it pioneered FinFET in 2011. This provides faster transistor switching speeds while achieving the same drive current as multiple fins in a smaller footprint.

Before then, the recent technology announcement renames the current 10nm process to Intel7, and the Intel4 process in 2022 with products in 2023 will compete with TSMC’s current 5nm process which will see an optical shrink to 4NP in the same timeframe. Intel3 will be ready to begin manufacturing products in the second half of 2023 using extreme ultraviolet (EUV) technology.

Beyond Intel 20A, Intel 18A 1.8nm equivalent is already in development for early 2025 with refinements to RibbonFET that will deliver another major jump in transistor performance. This is expected to use the High NA (numeric aperture) EUV process technology, and Intel expects to receive the first production tool in the industry from Dutch developer ASML. This will be key to reaching the 1nm node, but will also require new materials.

This will also include a shift from the 2.5D EMIB (embedded multi-die interconnect bridge) technology where the pitch of the connection uses real numbers. This will be the first dual-reticle-sized device in the industry, delivering nearly the same performance as a monolithic design, moving from a 55um bump pitch to 45um.

The Foveros 3D stacking technology will use a bump pitch of 36um, with tiles spanning multiple technology nodes and a thermal design power range from 5 to 125W. This will be followed by Foveros Omni that allows die disaggregation, mixing multiple top die tiles with multiple base tiles across mixed fab nodes and is expected to be ready for volume manufacturing in 2023.

Foveros Direct moves to direct copper-to-copper bonding for low-resistance interconnects with sub-10-micron bump pitches and blurs the boundary between where the wafer ends and where the package begins. Foveros Direct will enable a 10x increase in the interconnect density for 3D stacking, opening new concepts for functional die partitioning alongside Foveros Omni and is also expected to be ready in 2023.

www.intel.com

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