Several papers from Belgian research lab imec at the recent VLSI Symposium showed how a number of innovations are being combined to boost the scaling of chip design and the density of packaging by using the back of a chip..
Using buried power rails and thick via connections through a thin wafer help chips to scale, while planar capacitors and resistors can be added underneath the chip for decoupling between the die and a substrate in the package for even higher performance, says Geert Van der Plas, program manager at imec. The team is looking at building inductors, transformers and power transistors on the bottom of a chip to build a power converter for even higher power density.
“As an industry we have been struggling to scale chips, but our focus is increasing the power density,” he said. “The buried power rail allows the cell track height to scale so you can have a smaller cell height by 16 percent. That saves a lot of area but then you have to connect to the power rails. You can still do it on the front side but you need a via stack and that causes congestion. So we proposed accessing from the backside power delivery mechanism (PDM). This frees up the front side for the finer signals.”
“In 2019 we explored this with ARM but in this article [at the VLSI symposium] we looked at the different challenges to make it happen.”
“This backside PDM avoids going through the small vias on the front side and has robust metal all the way to the transistor with lower resistance so we have significant IR reduction from 60mV to 25mV,” he said.
For the through silicon via (TSV) to connect the power lines the team chose an aspect ratio of 5 which means a 500nm thickness of silicon for the wafer, which comes close to the bottom of the FinFET logic transistors that are already diffused in the wafer.
“It’s a few tens of nm below the FinFET, but the active part [of the FinFET] is quite high up. We did not detect a significant change in performance, and that suggests that the FinFet devices are not affected.”
“We are looking to increase power density and the decoupling is part of that so we have been working on ways to integrate high density capacitors,” he said.
This is a 2.5D structure in a 1um thick layer on top of the silicon wafer that act as a carrier for the thinned die. A silicon pillar creates the gap between the substrate and the die to build a metal-insulator-metal capacitor (or MIMCAP) that serves as a decoupling capacitor. This is used to stabilize the voltage supply by de-coupling the noise generated by the transistors switching activity. Having the MIMCAP in the wafer’s backside can reduce the supply ‘bounce’ with a factor of 15.
“You can do this in back end of line (BEOL) process with damascene layers and integrate these on the back side with the power delivery,” he said. “We found very significant benefits in reducing the ripple with a 15x improvement when we implemented the MIMCAP device, and this [also] allows down conversion,” he said.
One of the challenges is getting more current into the chip package by using a higher voltage and down converting the voltage at the chip. “For BGA packages we see the inductance itself is not a show stopper but it gets more difficult to get the current to the solder ball, its an ongoing debate but that’s why we looked at the down conversion in the package,” said Van der Plas. “If you down convert in the package there’s less current going through the solder balls. The main driver is getting more current into the package.”
“We investigated the design of a buck converter as well as a transformer,” he said. “An alternative approach would be a switched capacitor network, and we can use the same version of the capacitors from decoupling but with a thicker dielectric.”
The team developed an integrated MIMCAP as part of a charge pump that serves as a down-conversion integrated voltage regulator with 91.5 percent efficiency.
“We are also exploring magnetics,” he said. Transformer designs can handle higher voltage ratios than a capacitor which is 2, 3 or even 5:1. But converting 48V to 1V requires much higher ratios, and that needs a transformer.
“What we have done is integrated a ferrite core or a polymer matric in a reconstructed layer as an organic interposer at the wafer level,” he said., “We then use the copper on both sides and pillars to create windings to create a fully 3D solenoid inductors in a full wafer,” he said.
“What we did in the exploration is we combined the magnetic components with the circuit design. We are constrained by the thickness of the magnetic core as part of the down converter,” he said. “We need an area of 800um x 800um and we are constrained by the handling of the magnetic core, so if you put a larger size you won’t improve the power density as much.”
One of the issues is with the integrated down conversion is the cooling.
“I think it’s time that people start addressing this and people are looking at more disruptive cooling, with liquids or two phase cooling,” he said. “People are looking at several kW of TDP [thermal management] and that’s a 10x increase from today,” he said. Using the copper on the backside as a way to remove the heat is also under investigation.
The teams is also looking at how LDMOS power transistors can be add to the back of the chip to control the converters or for the I/O.
“We also thought we could use the backside for the switches that can handle 15V and I/O devices or core devices cannot support those voltages,” he said.
“We think there’s an opportunity to bring that power conversion elegantly into the stack. The idea was to have the diffusion from the front side as one of the first layers. This limits the thinness of the wafer. You can reserve an area for LDMOS but they could also be below the FinFETs, we considered both options,” he said.
All of this is bringing power conversion much closer to the logic transistors and higher voltages into the packages, highlighting a significant shift in the way chips, packages and boards will be designed in the future.
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