Bandwidth is key as Altera plans for the end of copper backplanes
Improving the I/O bandwidth to support 28Gbit/s backplane links and a new digital signal processing architecture that focuses on the bandwidth are both key elements of the 20nm products that will be launched next year with production in 2014 said Brad Howe, senior vice president of research and development at Altera.
But the move to 56Gb/s backplane technology is important as backplanes will move from copper to optical as a result, he says. “We think at 56G you won’t see copper backplanes anymore, it will be optical,” he said. “This is the interim step to 56G which is an architecture we have already put together.”
He sees it taking two to three years for the 56G standard to be settled, which sits well with the mainstream production of the 20nm technology. “It tends to play well with FPGA technology when the standard is in flux and we can help enable that industry,” he said.
The density and performance at 20nm now allows the capabilities to be on the die. “We are big believers in this being done monolithically as this provides signal integrity but we have done a fair bit of innovation in on chip instrumentation with an embedded eye viewer so you can see the performance of the link and logic analyser functions on the die.”
This embedded instrumentation is vital for getting the bandwidth performance and is a combination of hard and programmable elements, providing self-calibration and an adaptive engine to automatically optimise the bandwidth.
The new DSP architecture is also vital for making the most of the incoming data. “The DSP blocks have been re-architected for a more efficient implementation as well as the gains you would expect from 20nm,” said Howe. “I think in many ways our DSP architecture plateaued in prior generations and we haven’t pushed the boundaries because of the bandwidth, and we are now able to provide that.” The new architecture is providing five times the performance of the current 28nm devices with over 5TFLOP/s of single precision floating point DSP processing.
Despite a focus on monolithic devices, Howe also sees 3D stacking of chips as a key way forwards for more bandwidth. At the moment devices can be combined in a single package on a substrate in a 2.5D approach, but through silicon via technology is maturing to allow memory, ASIC devices (such as the Hardcopy ASIC versions of Altera FPGAs) and optical interface chips to be stacked on a FPGA die for a complete system in a package. The limiting factor is the ecosystem of packaging and test, he says. “Eventually we will get to TSV die but that won’t be mainstream for a while,” he said.
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