Battle of the multilayer flash chips
Following the launch of production of a flash memory chip with 232 layers by Micron last week, SK Hynix has announced a chip with 238 layers. At the same time, Chinese chip maker Yangtze Memory Technologies Co (YMTC) has announced a chip with 232 layers.
The 238-layer 512Gb NAND chip from SK Hynix uses three bits per cell (TLC) which with the multiple layers reduces the die size. The company says it has recently shipped samples of the chips customers with a plan to start mass production in the first half of 2023. A 1Tbit part is planned for next year as well.
“The latest achievement follows development of the 176-layer NAND product in December 2020,” said the company. “It is notable that the latest 238-layer product is most layered and smallest in area at the same time.”
“SK hynix secured global top-tier competitiveness in perspective of cost, performance and quality by introducing the 238-layer product based on its 4D NAND technologies,” said Jungdal Choi, Head of NAND Development at SK hynix in his keynote speech during the Flash Summit last week. “We will continue innovations to find breakthroughs in technological challenges.”
However the market is hugely competitive and Micro is linking up with customer Western Digital (WD), signing a memorandum of understanding to develop memory technology. WD also has an MoU with Samsung in the same way.
Since development of the 96-layer NAND product in 2018, SK hynix has used applied charge trap flash (CTF) and puts the peripheral circuits under the cell to make chips with what it calls 4D structure with a smaller cell area per unit than the previous designs.
Unlike floating gate, which stores electric charges in conductors, CTF stores electric charges in insulators, which eliminates interference between cells, improving read and write performance while reducing cell area per unit compared to floating gate technology.
The 238 layer chip is 34% smaller than the previous 176-layer device with a data-transfer speed of the 238-layer product is 2.4Gb per second, a 50% increase from the previous generation. The volume of the energy consumed for data reading has decreased by 21%.
The 238-layer products will be first used in solid state disks (SSD) for laptops before being provided for smartphones and high-capacity SSDs for servers later. The company will also introduce 238-layer products in 1 Terabit next year, with density doubled compared to the current 512Gb product.
The X3-9070 TLC 3D NAND flash from YMTC uses its Xtacking 3.0 architecture to build the layers for a 1Tbit chip.
This uses a 6-plane design with a synchronous multi-plane independent operation supported on each plane. Multiple and synchronized concurrency enhance system I/O performance on both sequential and random accesses. Compared to the typical 4-plane architecture, system performance can be boosted by up to 50% while power consumption can be reduced by 25%.
“The arrival of YMTC’s patented Xtacking 3.0 architecture is a breakthrough in the 3D NAND scaling race,” said Gregory Wong, Founder and Principal Analyst at Forward Insights. “The advancement of 3D NAND technology is crucial for innovation in the memory market, and as the most advanced flash memory to feature this type of architecture, the YMTC Xtacking 3.0 X3-9070 is a key industry milestone. In the future, hybrid bonding of memory cells and logic circuits is expected to become mainstream.”
“Tested and adopted across global markets, our Xtacking architecture is known to be the first of its kind and has been consistently empowering our clients and partners worldwide throughout its multiple generations,” said Thomas Chen, Executive Vice President of YMTC. “Following the milestone release of the X3-9070, we will continue to leverage our Xtacking technology in PCIe SSDs and UFS to ensure faster data access, shorter time to market, and lower costs per bit.”
www.skhynix.com; www.micron.com; www.ymtc.com
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