Beyond programmability: full design observability at runtime

Beyond programmability: full design observability at runtime

Technology News |
By eeNews Europe

Offered free of charge, integrated to version 3.0 of the company’s Stylus 3PLD design software, the so-called DesignInsight technology is said to deliver unprecedented levels of real-time device observability.

The new tool is intricately tied to the Spacetime architecture as it relies on the ABAX’ dedicated configuration network which itself has access to every individual node of the design, able to write or read them separately and access data at 2GHz (on the company’s latest 22nm ABAX2P1 devices). This gives designers 100% observability over the transactions taking place at every user logic nodes.

Assertions and conditional triggers can be set to buffer data from any given node in the design, pipelined through the configuration network.


The beauty of this solution is that users can observe signals in a production design operating at full speed without the need for recompilation or pre-declaration of target signals.

“This isn’t another Chipscope”, said jokingly Tabula’s Sr. Vice President and CMO Alain Bismuth, referring to Xilinx’ embeddable logic tracing tools. “If we have to set up debug logic points, we know where we’ll have issues, right? We would fix them before we ship.”

Typically in traditional FPGAs, 25 to 30% of user logic is destined to Quality-of-Service monitoring, explained Bismuth. With a technology such as DesignInsight, engineers could either reduce their die-size or have more logic available.

Through the combination of a programmable trigger unit and a configurable 1.3Mb trace buffer, users can observe any signal at full speed simultaneously over a maximum of 256 nodes in the design. The trace buffer can then be connected to any commercial visualization tool to look deeper into the signal and identify any faults.

“We are working to add more capability, with simultaneous visibility over a thousand nodes by 2015”, commented Andrea Olgiati, responsible for developing DesignInsight as he ran a demo of the tool for eeNews Europe.

Currently, the nodes to be observed in the design are chosen manually, but as a future tool development, Andrea plans to develop an automated node sweeping system capable of checking the entire design for correctness, based on a pre-determined design rules.

Because DesignInsight operates through a separate hardware fabric, on top of the actual reprogrammable logic layer, it does not require any interruption of the system in order to change views (collections of signals to be monitored) from one set of signals to another. New assertions written in SystemVerilog can be created and compiled in minutes and applied to the design transparently during normal device operation, even in systems deployed in the field.

Pre-compiled DesignInsight views are also delivered with all of Tabula’s 100G pre-engineered solutions, providing users with examples of how the technology can provide visibility into key elements of these solutions. This dramatically reduces R&D costs and CAPEX for customers, since maintenance and in-depth diagnostics can be performed remotely, no need to take the board off-line.

“From the very beginning of creating the Spacetime programmable logic architecture, our goal was to rethink the user interfaces and the user experience of programmable logic”, commented Tabula’s founder and CTO Steve Teig.

“We wanted to have observability without compromise, being able to design well and see everything from the design start to the fully functional product.”

“Typically, once a design is in silicon, all the verification views are thrown away. While fixing the actual bugs is usually easy, 80 to 90% of the debugging time is spent finding where they are. We want to make that 80 to 90% phase shrink significantly.” Teig added.


Full design observability is maintained throughout the Tabula design flow.

“After Spacetime and delivering functional hardware, DesignInsight is the second big development on Tabula’s roadmap, with a third announcement yet to come”, said Teig who has had all three developments clearly lined-up in his mind since founding the company, declining to say more about the road ahead.

“The capability was always there, it is just that as a small company, we had to focus first on proving the Spacetime architecture with actual chips before we could spend resources on developing DesignInsight for our customers” clarified Bismuth.

Related news:

Tabula introduces 3-dimensional Spacetime programmable logic architecture

Tabula takes on FPGA vendors with four channel 100G networking chip

Stealthy Tabula has raised cash for PLD launch

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