Bits from Hot Chips: Robots, Cisco, Oracle

Bits from Hot Chips: Robots, Cisco, Oracle

Technology News |
By eeNews Europe

"As an industry we’ve basically saturated what you can do with a robot behind a cage for industrial uses—the next 50 years will be about personal robots," said Steve Cousins, chief executive of Willow Garage, in a keynote describing and demonstrating the company’s latest robot.

A video of his demo is online on YouTube here.

The robot uses two eight-core Intel Westmere processors in its base and a Microsoft Kinect sensor on its head as a navigation aid. The components are less than ideal.

The processors require a loud fan for cooling and are easily swamped by still nascent programs for object recognition and robot decision making. The Kinect is useful but "we need better sensors—it’s hard to get a camera that’s even close to what the human eye sees," said Cousins.

Besides the Kinect, the robot uses nine video cameras and two laser scanners taken from garage door controllers. "All we get are hand-me-downs," said Cousins.

He called for low power, high performance processors that support large shared memory operations. He also called for specialized processors that could work in tandem with a variety of touch and camera sensors.

For its part, Oracle gave the first look inside the T4, a next generation Niagara family server processor using a new out-of-order, dual-issue core. Engineers got a stunning five-fold integer and seven-fold floating point boost on the T4, despite ratcheting back from 16-cores on the previous T3 versus just eight cores on the new chip.

Oracle’s T4 uses a new dual-issue core that accepts eight threads.

Oracle is continuing its aggressive support of eight threads per core, started under the former Sun Microsystems. "We think we still lead in threads per chip, and we will continue to do so," said Robert Golla, a senior hardware architect at Oracle.

The new S3 core will be the basis for future Oracle processors. It sports extensive new branch prediction and pre-fetch features, a new dynamic threading approach for mixed workloads and a 16-stage integer pipeline running at more than 3 GHz. The core adds a handful of new instructions to boost performance on cryptography and some Oracle-specific apps.

Except for a new crossbar and cache design, the 40nm TSMC chip uses similar blocks as the prior T3 chip. The T4 has been running in lab all year but has not yet been released in systems.

Finally, Cisco Systems described Sereno, a 40 Gbit/s Ethernet ASIC it will use in its next-generation servers. The chip includes a mix of virtualization and networking features not found in merchant chips, Cisco engineers said.

Popular systems software such as Microsoft Windows Server and VMWare’s ESX do not support the so-called SR-IOV virtualization defined by the PCI Special Interest Group. So Cisco designers created their own I/O virtualization technology for its chip, letting it act as up to 256 Ethernet virtual interfaces to the system, each with its own VLANs, multicast, filters and other capabilities.

The chip includes a MIPS R24K processor to handle network management jobs, including tracking up to 16 million network flows, offloading work from the server host CPU. The chip also groups its interrupts so as not to generate "interrupt storms" that swamp the host processor.

The 65nm chip was made at Texas Instruments, is running in the lab and going through system-level testing to ship with future Cisco servers.

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