Boost ADC performance at Gsample rates, with digital enhancement

Boost ADC performance at Gsample rates, with digital enhancement

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By eeNews Europe

When pushing the sampling rates of high-resolution analogus-to-digital converters (ADCs) into the Giga samples per second range, the limit of what can be achieved with single-core ADC implementations is quickly approached. The solution to further increase the sampling frequency is to time-interleave several ADC cores whereby the ADC cores take turns in converting samples into digital format.

However, when time-interleaving several ADCs, differences in gain and phase-response (including time-skew), as well as DC offset between the individual ADCs, produce nonlinear distortion called aliasing that is typically the main performance limitation of time-interleaved ADC arrays. These differences are usually referred to as mismatch errors and are very challenging to remove by purely analogue design [refinements] and careful circuit layout. As an example, in order for a 4 Gsample/sec time-interleaved ADC to achieve 80 dB spurious-free-dynamic-range (SFDR) for a 2 GHz input signal, a time-skew less than 8 fsec is required – a time alignment so short that it corresponds to the propagation delay of a wire length of 1.2 mm.

The figure shows a comparison of three different Gsample/sec time-interleaved ADCs with respect to unwanted aliasing spurs generated due to mismatch. The ADCs used in this test are the Analog Devices AD9625 (2.5 Gsample/sec, 12-bit resolution), Texas Instruments ADC12J4000 (4.0 Gsample/sec, 12-bit resolution), and the E2V EV10AQ190 (5 Gsample/sec, 10-bit resolution). The broken lines represent the “raw” performance of each device. As can be seen, the unwanted aliasing spur levels differ between the different ADCs but common to all time-interleaved ADCs in general is the fact that effects of phase-response mismatches (and time-skew) grow worse with frequency. This is clear from the measurement results in the figure. It should also be noted that the AD9625 operates at a lower sampling rate than the ADC12J4000 and the EV10AQ190 and therefore the mismatch spur level comparison is made over two Nyquist bands for this device.

With digital mismatch error correction the mismatch errors can be handled even when the errors vary over frequency. Such error correction can equalise the differences between all the ADCs to such a small level that the unwanted aliasing spurs are suppressed down to the noise floor. The figure shows the results when the ADX4 digital time-interleaved ADC mismatch error correction IP-core is used to enhance the ADCs. The performance of all three ADCs, says SP Devices, can be improved significantly with ADX4. While the AD9625 can be enhanced to the highest performance level, even the 10-bit EV10AQ190 can surpass the 12-bit alternatives AD9625 and ADC12J4000 in their native state if enhanced by ADX4.

The differences in the level of performance enhancement that can be achieved for each device is, SP Devices concludes, mainly due to overall noise levels and the properties of the noise contribution to the individual ADCs.

SP Devices;

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