Bottom up approach yields atomic-thin FinFETs

Bottom up approach yields atomic-thin FinFETs

Technology News |
By eeNews Europe

Now a team of researchers from the Institute of Metal Research (IMR) of the Chinese Academy of Sciences and CEA Leti in France has found a way to further shrink the fin’s width beyond what’s achievable with traditional top-down fabrication methods. Indeed, in most FinFETs, the fin channel is etched from a bulk plane, with the width inherently limited by the precision of state-of-the-art lithography tools.

The ML-TMD fin as compared to etched Si-fin and nanotubes
in their typical dimensions (top left). Schematic picture of the
ML-FinFET (bottom). The inset shows several options for
depositing the fin materials in this structure.

As described in a Nature Communication paper titled “A FinFET with one atomic layer channel”, the researchers have opted for a bottom-up manufacturing approach to replace the conventional Si-based fin with an atomic-thin monolayer of a MoS2, a 2D-material.

To do so, the researchers designed a wet-sprayed chemical vapor deposition (CVD) method to universally grow monolayers of transition metal dichalcogenides (ML-TMD) such as MoS2 and WS2 on step-shaped templates. Thanks to this bottom-up fabrication approach, the researchers were able to design vertically free-standing 2D MoS2 and WS2 monolayers which they conformally coated with insulating dielectric and metallic gate electrodes, pushing the FinFET to the sub 1nm fin-width limit.

False-coloured SEM image of an ML-Fin array, with a 50nm
pitch and 300nm fin height. Scale bar is 300nm.

The paper reports monolayer FinFET structure with a record-breaking fin width of 0.6nm, capable of on/off ratios reaching about 107, with a sub-threshold swing of about 300mV/dec and mobilities on the order of a few cm2V-1s-1. The authors also demonstrated fin-arrays with a minimum pitch of 50nm. They note that in the future, gate electrodes could also be made of a carbon nanotube thin film to shrink the whole device.

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