Bridging the gap between speed and power in asynchronous SRAMs
The Asynchronous SRAM space is divided between two very distinct product families – fast and low power – each with its own set of features, applications, and price. Fast Asynchronous SRAMs have faster access time, but consume more power. Low-power SRAMs save on power consumption, but have slower access time.
From a technological standpoint such a trade-off is justifiable. In low-power SRAMs, special Gate-induced Drain Leakage (GIDL) control techniques are employed to control stand-by current and thus standby power consumption. These techniques involve adding extra transistors in the pull-up or pull-down path, as a result of which access delay increases hence increasing access time. In Fast SRAMs, access time is the highest priority and hence such techniques cannot be used. Moreover, the transistors are scaled up in size to increase charge flow. This scaling-up reduces propagation delay but at the same time increases power consumption.
From the standpoint of application requirements, this trade-off has led to two distinct application bases. Fast SRAMs work well as a direct interface cache or scratchpad expansion memory for high-speed processors. Low-Power Asynchronous SRAMs are used to temporarily store data in systems where power consumption needs to be very low. Hence, while Fast SRAMs are typically used in high performance systems like servers and aeronautical devices, Low-Power SRAMs are used most in battery-powered devices like POS terminals and PLCs.
However, technological advancement is driving more wired devices to battery-backed mobile versions. For the past few years, we have also been witnessing the introduction of a plethora of wireless applications leading to a wireless gadget boom. This new generation of medical devices, handheld devices, consumer electronics products, communication systems and industrial controllers, all driven by the Internet of Things (IoT), is revolutionizing the way devices function and communicate. In such mobile devices, both Fast and Low-power SRAMs fail to service the need comprehensively. Fast SRAMs have high current consumption and thus drain the battery too quickly. Low-power SRAMs are not fast enough to handle the demands of such complex devices.
For all key components of modern electronic devices, reducing power consumption and footprint are two of the biggest challenges at hand. For Asynchronous SRAMs, the challenge translates to creating a Fast SRAM that consumes considerably less power, all in a small footprint. While many SRAM manufacturers have started offering products in small pin-count and die-sized packages, the demand for low-power high-performance memory hasn’t been met.
Power management and stand-by power
There are two major parameters that define the power consumption of a device – operating power and standby power. Operating power is the power consumed when a device is actively performing its primary function. In the case of SRAMs, this would be the power consumed during a read or write function. Standby power is the power consumed when the device is not active but is still powered on. On a large majority of handheld devices, SRAMs are in operation around only 20% of the time.
The remaining 80% of time, SRAMs are connected to the power source in standby mode. In the days when most electronic devices were connected to a power outlet, standby power consumption was not much of an issue in terms of cost or convenience. However, for today’s battery-backed devices, standby power adds a considerable power premium. If the source of power is a non-rechargeable battery, then that would lead to faster battery burnout. In the case of rechargeable batteries, the major concern happens to be inconvenience – the very purpose of a mobile device is defeated if it has to be charged too often.
The need for lower power consumption hit microcontrollers the earliest, forcing manufacturers to find alternatives to the traditional two -tate mode – active and standby. This led such companies as TI and NXP to introduce MCUs with a special low-power mode of operation called deep power down or deep sleep. These controllers run at full speed during normal operation but go into low-power mode when not required. That way, systems can reduce power consumption without compromising on high performance. During this low-power mode, peripherals and memory devices are also expected to save power. The onus of power management has now shifted to memory devices interfaced to such systems.
SRAMs with on-chip power management
Before we describe the concept and possibilities of SRAM with on-chip power management, let us first understand why it is the need of the hour. On an electronic board, an asynchronous SRAM typically interfaces with the MCU as an expansion memory that can work as a cache or a scratchpad memory. Compared to other storage memories like DRAM and Flash, SRAM is limited in terms of density (the highest density SRAM available today is 8MB, while DRAMs are available in GBs). However, it is difficult for an MCU to interface directly with a DRAM or Flash as these memories typically have long write cycles and are unable to keep pace with the MCU. An MCU that operates at high speed thus needs a cache that can store critical data and temporary calculations in a way that can be accessed quickly. SRAM is best fit to act as a cache between the MCU and storage memory.
The following diagram better explains the different stages of memory, and where an SRAM is needed:
The need for a power-efficient fast SRAM is further propelled by the following factors:
- The role of embedded cache is getting increasingly limited in modern MCUs with every new process node.
- External cache is becoming more important because of the above factors and also because MCUs are becoming more advanced. Thus, it is imperative that SRAMs aren’t a limiting factor.
- In battery-backed applications, power-consumption is an important parameter that customers consider during purchase. Thus high standby power consumption by an SRAM chip is not acceptable.
Considering all the above factors, SRAM manufacturers have tried over the years to limit the trade-off between Fast and Low-power products. One of those solutions is a hybrid device, midway between fast and low power in both access time and power consumption. However, these hybrid SRAMs are unable to meet the performance requirements expected from Fast SRAMs. The best solution is a Fast SRAM with on-chip power management, ensuring both high-performance and low-power.
SRAMs with on-chip power management work in a similar way to MCUs with on-chip power management. Apart from the active and standby modes of operation there is also a deep-sleep mode of operation. Such a set-up allows the SRAM chip to access data at full speed during standard mode of operation while during deep-sleep the device doesn’t perform any functions but the current consumption is extremely low (1000 times less than standby consumption of usual Fast SRAM).
The following table compares the various parameters of a Fast SRAM, Low Power SRAM and a Fast SRAM with deep-sleep mode of operation:
The numbers clearly demonstrate the advantage of using a “Fast with Deep-Sleep” SRAM over a standard Fast SRAM. The advantage will be more prominent in applications where the SRAM is on standby most the time.
Let’s consider a hypothetical scenario: A device functions for thousand hours during which the SRAM is operational for only 20% of the time. If the SRAM is a Fast SRAM operating at 3.3V, it will consume 120 Watt-Hour (WH) during operation and 80 WH during standby. Total energy consumption would be 200 WH. Now if we use a Fast SRAM with Deep-Sleep instead, the energy consumption during operation remains 120 WH but the consumption during standby comes down to 0.06 WH. The total energy consumption is around 121 WH. Thus in this particular case, the Deep-Sleep option lowers energy consumption by 40%. There is, however, one factor to consider when using deep-sleep mode (be it MCU or SRAM) – the time taken to enter and exit deep-sleep mode. If the time interval between two active periods is too short in comparison to the time taken by the SRAM to enter or come out of deep-sleep mode, then the method will not be useful.
Today, PowerSnoozeT, PowerSnooze SRAMs have on-chip power management, and come in the same standard packages as regular fast SRAMs (such as 54-TSOP & 48-BGA). To use the deep-sleep functionality, there is a special pin (DS), which is toggled active low to enter deep-sleep mode. The equivalent pin on a standard Fast SRAM happens to be NC (no-connect). Thus, to upgrade from a standard Fast SRAM to a PowerSnooze SRAM only minimal design effort is required (there is one extra pin to be interfaced).
To know more about on-chip power management in Fast Asynchronous SRAMs you can check out the following application note: https://www.cypress.com/?docID=48906.
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