Bringing advanced medical technology up to speed

Bringing advanced medical technology up to speed

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By eeNews Europe

Consumer electronics have taken great strides forward over the past decade in terms of affordability, size and power. In contrast, medical electronics has yet to experience a similar type of innovation. However, an increasing world population, longer life expectancy and rising standards of living should become catalysts for a medical devices revolution that will help improve general wellbeing while reducing healthcare costs.

The following are some key design challenges for medical electronics designers:

1. Features differentiation – Competition is increasing within medical electronics markets, as attractive margins drive various manufacturers to deliver products with differentiating features and advanced performance to stay ahead of other contenders.

2. Power reduction – There will be a tight power budget ahead for medical devices as future medical electronics prioritise wireless operation and focus on miniaturisation. Reducing power consumption can lead to better thermal management thus reducing overall product size.

3. Development time – Medical electronic devices must pass a lengthy certification process which can significantly slow down time to market. The typical development cycle for consumer electronics products is 3 to 9 months, whereas typical medical electronics average 2-3 years. Tools and methods available to reduce development time and aid in certification will be vital.

These challenges can cause engineers to make unwanted tradeoffs between features and cost, or power and size. The design of ultrasound equipment provides a prime example.

Ultrasound imaging

Due to its non-invasive nature, ultrasound imaging is used across many medical applications from diagnostic investigations to therapy. High-performance ultrasound machines offering the highest resolution and state of the art 4D image viewing are still cart-based and bulky. On the other hand, portable or handheld versions have significant limitations in terms of battery life and image quality. Clearly the performance-to-size ratio still needs to be improved. One could envision a future in which personal ultrasound machines could be marketed to expectant parents. For this to happen, however, the equipment would have to reach consumer-level pricing, portability and ease of use. We may be a few years away from realisation of such product, but what are the products and platforms that can help solve the design challenges of medical designers and improve the performance/size or performance/price ratio?

For many years Field Programmable Gate Arrays (FPGAs) have been central to the enablement of medical ultrasound technology. FPGAs have a long product life cycle which can match the long time-in-market requirement for medical electronics. Performance and flexibility are two primary attributes that make FPGAs the device of choice for ultrasound imaging. By allowing algorithms and features to be updated without needing to change-out components, FPGAs enable systems to become essentially future-proof. With every technology node shrink, FPGAs provide increased performance to price ratio; for example moving from 28nm to 20nm can result in 20-50% performance improvement while also reducing power consumption. In addition, FPGA tools support an abstracted design flow, performing automated timing closure and minimising place-and-route time, leading ultimately to shorter development time. By continuing to provide such advantages, FPGAs will remain critical to the design of next-generation ultrasound equipment.

Let’s explore how to satisfy the functional requirements of a medical ultrasound system. An ultrasound imaging system can be split into three main functions: front-end, transmission, and back-end. Programmable technology such as FPGAs plays a crucial role in each of these blocks.

Figure 1: The ultrasound system data path consists of several key components that can benefit from FPGA properties

The objective of an ultrasound front end is to control transmission of ultrasonic pulses and capture the reflected sound data. Analogue-to-Digital Converters (ADCs) convert the reflected ultrasonic data into digital format. Most of the ADCs used in ultrasound imaging applications support from four to eight channels and 12-16 bits resolution at 40-60 Msamples/sec. Cart-based ultrasounds require high resolution, often with as many as 128 or even 512 channels, whereas a portable ultrasound that must meet low weight and size targets may have as few as eight channels. In order to support the high volume of data transmission, ADC outputs typically use Low Voltage Differential Signalling (LVDS). Because an FPGA has large number of input/output (IO) blocks which can be configured to support LVDS, it can aggregate data from several ADCs for pre-processing.

Manufacturers seeking the highest scan resolution are pushing the limits in terms of the number of channels that can be supported, to handle high volumes of data. To alleviate this, several ADC manufacturers have adopted the JESD204B standard as the new serial protocol to support data transmission at Gbit/sec rates. A JESD204B receiver configured inside the FPGA allows data to be received from the ADC at up to 12.5 Gbit/sec per lane.


Figure 2 JESD204B in FPGAs support higher bandwidth performance at reduced IO count

Beam forming is a mechanism to control the sound pulse to amplify the key area of focus and de-emphasise the non-relevant areas, and is considered to be critical in an ultrasound system. In fact many companies customise and protect their beam forming technique to gain a competitive edge. Beam forming involves computation in both the space and time domains, with dynamic configuration to locate the focus point. To perform the required computations efficiently, digital beam forming is displacing traditional analogue techniques. The flexible hardware structure and DSP-intensive architecture of today’s FPGAs enables complex beam forming computations to be executed quickly and efficiently.

Finally, pre-processing comprises a wide range of data manipulation, such as gain compensation, filtering, data enhancement and more. These algorithms are implemented as custom functions inside FPGAs in order to process large sets of data in real-time.

Programmable technologies save power

Power consumption is often a key concern in ultrasound imaging, especially portable equipment which is limited by a fixed battery pack. Although power is not as critical in a corded system, the thermal issues related to power dissipation and power-cycle management must still be considered when making engineering decisions. An FPGA fabricated in 20nm technology will have 20% to 50% lower overall power (dynamic, static and IO power combined) compared to 28nm technology. The dynamic and static power savings will become an advantage in both the system front end and back end, as beam forming and image reconstruction are compute intensive processes. In addition, a 30% reduction in the power dissipated by transceivers and IOs will result from use of in transmission functions within ultrasound machines. Their technology allows various power-down modes for different blocks for optimal system efficiency. The reduced power consumption of a 20nm FPGA, combined with intelligent power management, provides extra margin for engineers to increase system performance and enhance resolution without exceeding the total power budget.

All-programmable abstraction flow reduces development time

The final block within the signal chain of the ultrasound system performs image reconstruction, which translates the raw data captured by the front end into an image which can be displayed on a monitor. There are many algorithms written in C, C++, MATLAB, or OpenCL that determine how the acquired data will be processed, converted, and interpreted into a viewable image. This step involves complex matrix multiplication involving computationally intensive Fast Fourier Transforms (FFT). Often software engineers build models of the necessary algorithms, and hardware engineers translate these to Hardware Description Language (HDL) for implementation in the FPGA. This division of activity causes a disconnect in the design flow which can increase development time, particularly when several design iterations are needed.

A solution is an all-programmable abstraction tool: a tool that automatically converts C, C++, OpenCL or MATLAB constructs into HDL, and automatically places and routes the design into the FPGAs. This can result in up to 15-times shorter development time compared to a conventional manual design flow, thereby enabling medical technology designers to focus on core competencies in image construction and interpretation.

As FPGA technology matures with increased performance, reduced power and shortened development time, we can look forward to a future with next-generation ultrasound imaging systems offering the advantages of improved scanning resolution and convenient portability, at an affordable price.


Figure 3 Implementing ultrasound front end, pre-processing, transmission and backend image reconstruction using FPGAs

Yvonne Lin is Medical Marketing Manager at Xilinx.

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