Broadcom preps for 7nm tape-outs in 2017
The IP cores include high 112Gbit/s PAM-4 SerDes, high-bandwidth memory PHY, Die2Die interconnect PHY, mixed-signal IP, and foundation IP such as standard cells, SRAM, TCAM memory, and I/O cells. Theses cores, proven in silicon with TSMC, are due to be used in ASICs for deep learning and networking applications.
The interface IP includes JEDEC-compliant HBM Gen2 and HBM Gen3 PHY provide and a portfolio of ARM cores and peripherals. The design kit for 7nm ASICs is available now and several customer products are already in development. Lead 7nm customer ASIC products are scheduled to tape-out in calendar Q4 2017.
“TSMC 7nm process technology and CoWoS technologies combined with Broadcom’s IP cores and ASIC design methodology continues to enable best-in-class custom solutions for the end customers,” said B J Woo, vice president of business development at TSMC, in a statement issued by Broadcom.
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