Brush up on the theory before designing a high power Class‐E amplifier

Technology News | June 29, 2016

By Jean-Pierre Joosting

1. Abstract

This article covers the Class-E theoretical basis initially introduced in the 1970’s by Dr. N.O. Sokal and A.D. Sokal (1) and the idealized operation mathematically explained by Dr. Raab (2). Then we’ll discuss the effects caused by the various non-ideal effects present in the circuit (3), and finally, we’ll present a 500-W class-E amplifier designed with two SD4933 from STMicroelectronics in parallel.

For Class-E amplifiers, the theory offers useful equations for starting a new design, all obtained by making mathematical assumptions for the voltage at the device’s drain and considering lossless components. Nevertheless when all these hypotheses are gradually removed, it’s difficult to obtain closed-form equations, and the circuit analysis can be done using Electronic Design Automation software (EDA).

2. Idealized Class‐E operation

The basic form of a Class-E power amplifier is shown in Figure 1. The topology consists of a transistor, a shunt capacitor C, RF choke L₁, and a series L₂-C₂ resonator followed by the load resistance R.

The Class-E amplifier works in switched mode — the transistor is driven hard enough to saturate in order to act as a switch with two discrete states, ON and OFF. The circuit operation is determined by the transistor when it is ON and by the transient response of the load network when the transistor is OFF. The previous circuit is equivalent to the one shown in Figure 2.

Figure 2: Equivalent schematic of the Class-E circuit.

In Figure 2, the transistor has been replaced by a switch—the capacitor C₁ comprises the external capacitance, C, and the transistor’s output capacitance. The series combination L₂-C₂ is tuned at the frequency of operation ω_c. Moreover, the series reactance jX (at the switching frequency f_sw) can model a circuit mistuning or a change of the operating frequency.

3. Basic assumptions for a Class‐E amplifier

Generally the analysis of the circuit is done with the ideal simplified assumptions:

The transistor is an ideal switch, i.e. a short circuit in the ON state and an open circuit in the OFF state, with an instant switching action.
The switch is operated with a 50 % duty cycle, at the switching frequency.
The switch can sustain the current running through it in the ON state and also must be able to stand the non-zero voltage that appears during the OFF state.
The RF choke (DC-feeder) has a very large inductance and accordingly allows only DC current to flow through it.
The loaded Q-factor (QL) of the series resonator L2-C2 is high enough so it can be considered that a purely sinusoidal current is running through the load R.

3.1. Design equations for infinite QL

Under the above ideal conditions, it’s possible to obtain design equations for each component of the circuits. It’s hypothesized that the circuit has reached a steady-state operation and the RF ON-OFF cycles are equally divided.

In Figure 3 are displayed the well-known ideal Class E waveforms in the switch, plus the shunt current through the capacitor C1.

From now on, the angular phase is defined as Ө = ωt with ω as the operation frequency.

Due to the large reactance of the RF choke at the frequency of operation, we can consider that only DC current IDC flows from the power supply. Moreover with the assumption of QL = ∞ for the series resonator, L₂-C₂, only the fundamental frequency current can flow through the load.

The current delivered to the load R is:

i_R(θ) = I₁sin(θ + φ) → Equation 1.

Where I₁ denotes the amplitude of the load current and φ is the initial phase.

At OFF state, the currents flowing through switch and shunt capacitor C1 are:

i_sw(θ) = 0 → Equation 2,

i_C(θ) = I_DC – I₁sin(θ + φ) → Equation 3.

The current i_C(θ) is charging / discharging the shunt capacitor C₁ (see Figure 2). Since we assume that during the ON state the voltage across switch/shunt capacitor is equal to zero, the capacitor voltage in the OFF state can be found as:

→ Equation 4

If we substitute Equation 3 into Equation 4 and perform the integration in the given boundaries, we will find that the capacitor voltage at any instant in the OFF state is given by:

→ Equation 5

A feature of the Class-E operation that distinguishes this class from other switching-mode PA configurations is the so-called “soft switching.” In other words, the switch closes precisely at the instant where the shunt capacitor is completely discharged.

Therefore, to achieve the soft switching at the drain voltage, at the turn ON the output’s network must force the electrical boundary conditions as initially introduced by Sokal:

→ Equation 6

→ Equation 7

After some calculations, each component of the output network can be found by the following equations:

→ Equation 8

→ Equation 9

P_DC and R_DC are respectively the power absorbed from the power supply totally delivered to the load and the resistances the DC supply sees. The idealized model already presented in addition with the boundary conditions (Equation 6 and Equation 7) produces a theoretical power efficiency of 100%. In reality, the power efficiency will decrease because the ideal assumptions are not met and also because we must add the power losses of each component.

3.2. Device’s electrical stress

The output capacitance C₁ reaches the max voltage when its current becomes zero (Figure 3):

i_C(θ_m) = 0 → Equation 11

From Equation 3 follows:

I_DC – I₁sin(θ_m + φ) = 0 → Equation 12

Using the boundary conditions for class-E (Equation 6 and Equation 7) in Equation 5 (voltage across C1) we get:

I_DC = (2/π)cosφI₁ → Equation 13

I_DC = sinφI₁ → Equation 14

Comparing the two equations, for a duty cycle of 50%, we obtain:

φ = arctan(-2/π) = 0.563 rad → Equation 15

In Equation 12 replacing IDC with Equation 14, we get:

sin(θ_m + φ) + sin(φ) = 0 → Equation 16

Using the Prosthaphaeresis identities, we get:

θ_m = -2φ → Equation 17

Finally, we obtained the popular equations for peak voltage and current for the active device:

V_pk = V_c(θ_m)= 2πφV_DC = 3.562V_DC → Equation 18

I_pk = I_DC + I₁ = I_DC – I_DC/sinφ = 2.862I_DC → Equation 19

For a duty-cycle of 50%, the peak voltage at the drain terminal exceeds the supply voltage of the circuit by more than three times.

Dr. Raab in (2) has presented all the equations that govern an idealized Class-E RF power amplifier. In particular, he has proved that a duty-cycle of 50% represents an optimum in terms of output power capability. Moreover, the device’s breakdown voltage determines the maximum allowable supply voltage and it is in direct relation to the output power.

3.3. Design equations for finite QL

When Q_L (defined as 2πfL₂/R) decreases, the above equations progressively produce less accurate results.

In some cases, Dr. Raab’s equations (2) have been represented in tabular form with the output power, C₁ and C₂ as function of Q_L.

Table 1: Tabular Raab’s equations versus Q_L.

Even if Q_L is a free-choice design variable from the theory, it must satisfy the condition Q_L ≥ 1.7879; when Q_L = ∞ we may recognize the results already found.

In (4) Dr. Sokal found compact design equations representing the data shown in Table 1 using polynomial functions in Q_L.

→ Equation 20

→ Equation 21

→ Equation 22

L₂ = Q_LR/ω → Equation 23

3.4. Finite DC‐feed inductance

Using a finite DC feed inductance instead of an RF-choke has significant benefits (5), (6):

Higher load resistance then less losses on the output matching network (7).
Possibility to use devices with lower breakdown voltage.

To analyze a circuit with DC finite feed, the inductance is quite complex, and a practical approach (3) is to choose the RF choke reactance higher in comparison to the reactance of the shunting capacitor, i.e.,

→ Equation 24

→ Equation 25

4. Design a 500 W Class‐E at 13.56 MHz

The target specifications for the design are shown in the table below.

4.1 Device selection and circuit simulation

Using the Advanced Design System (ADS) from Keysight (Agilent), we have analyzed the RF performances of the switch mode Class-E power amplifier. The analysis of the circuit was done using the transient envelope and the harmonic balance simulation. With the transient envelope, we optimized the values of the output components (Figure 4) in Class-E conditions (Equation 6, Equation 7).

Figure 4: Transient envelope simulation.

In simulation, we implemented Equation 20, Equation 21, and Equation 22, with capacitors and inductors lossless and loaded quality factor Q_L (resonant load) chosen as high as 10. The measurement equations include the conditions when the switch voltage and its voltage derivative is zero just before the switch is turned ON. In order to reach the steady-state condition and check the Class-E conditions, 20 periods were considered.

Figure 5: Transient to reach the steady-state.

Figure 6: Zoom of transient at 20th period.

To evaluate the relationship between the device’s R_DS(on) and the required R_load required from theoretical Class-E, we performed a switching voltage simulation at different coefficient factors: R_load_factor defined as ratio between the R_DS(on) and the R_load (Figure 6).

At switch-ON, the Class-E conditions were met with R_load_factor = 0.03 and R_DS(on) = 82 mΩ. In Figure 7 and Figure 8 are shown voltage and current with the value of the components optimized.

Figure 7: Current waveform of the MOSFET.

For the project, we selected the SD4933 from STMicroelectronics. The device is a 50-V N-channel MOS field-effect RF power transistor specially designed for ISM applications up to 100 MHz (7). Since the SD4933 has R_DS(on) = 170 mΩ at I_D = 20 A, using two devices in parallel gave us R_DS(on) = 85 mΩ, which is similar to the value obtained before.

In simulation, we found a drain peak voltage of 173 V; this value is compatible with the breakdown voltage reported in the datasheet of SD4933.

In order to get an amplifier with high efficiency we estimated the losses of each component. To build the amplifier, we used ATC 100B capacitors with high Q. To minimize the total losses, we used multiple capacitors in parallel (C₁ and C₂), and for them we estimated an equivalent ESR = 5 mΩ. The wire wound inductors used in the amplifier were handmade; we did preliminary trials to obtain an ESR = 100 mΩ for each of them.

Implementing the equations for Class-E plus the device’s losses inside the harmonic balance (Figure 9), we obtained the following results (Figures 10 and 11).

From simulation, we got an efficiency of 93.4% and a power out of 512 W at 13.56 MHz (Figure 12). Using two SD4933 in parallel, we have halved the R_DS(on) and the stray inductances, but we doubled the equivalent capacitance C_oss.

At this point of the design, the nonlinear characteristic of the C_oss versus the drain voltage was under particular consideration.

To depower the negative effects of C_oss, we introduced the advantages offered by the finite feed inductor already introduced.

Two SD4933 in parallel at V_DS=0 have an equivalent C_oss= 800 pF. Instead of considering two devices in parallel as an equivalent single device, we decide to address the two C_oss separately. At the drain’s leads of each SD4933 we added external ceramic capacitors in parallel; the value of these capacitors has been chosen to be about one half of the C_oss. These additional capacitors have a balancing effect against the nonlinearity of C_oss. Moreover, the finite feed inductor (dynamically in parallel with the drains) helps to reduce the impedance’s module without changing the capacitive behavior of the impedance (a new C₁ in Figure 2). This new C₁ with reduced value and better linearity is the capacitance at the entrance of the resonant output thanks to C₂-L₂ (see Figure 2).

4.2 Gate driver

Dedicated consideration was given to the current gate driver’s capabilities and its role on the overall device efficiency. In order to drive two SD4933 in parallel, we used a gate driver with a high peak current capability like the DEIC515 from IXYS (8). This gate driver can source and sink 15 A of peak current while producing voltage rise and fall times of less than 4 ns, and minimum pulse widths of 8 ns.

4.3 Prototype and RF performances

The schematic and the BOM of the project are presented here:

After an extensive hands-on lab activity was required to refine the RF performances of the power amplifier, the results are here shown. In Figure 14, we see Pout and the Efficiency versus the supply voltage. When Vdd= 50 V, the Pout reach 500 W while the Efficiency settles to 88%, which is slightly lower than expected.

Figure 14: Pout and Efficiency versus VDD.

Figure 15: Drain Current and Voltage Peak versus VDD.

In Figure 15, we can see the peak current and voltage at the device’s drain. When Vdd = 50 V, we can see that the drain peak voltage is a little bit higher than expected from the theory; however, the value is still inside the device’s specification.

In Figure 16 is shown the demo of the amplifier, and in Figure 17, the finite feed inductor made with thin copper is visible located on the back side of the board.

Figure 17: Finite Feed-Inductor beneath the Demoboard.

Conclusion

This article has discussed the theoretical guidelines and the practical aspects for synthesizing the matching networks of a high power RF class-E amplifier. The performance of a SD4933 from STMicroelectronics has been studied thoroughly. It was shown that the high efficiency operation of such amplifiers is determined mainly by the output load network.

Despite the fact that the power efficiency is a little bit lower than expected (declared at the beginning of the design), we deem that with a different gate drive and a proper input matching network, the performance of the amplifier can be substantially improved.

About the authors

Alfio Scuto (alfio.scuto@st.com) received the Master’s degree in Microelectronics engineering from the University of Catania, Italy. In 1999 he joined the STMicroelectronics RF Power Design Center in Montgomeryville (PA) USA. As an RF Application Engineer he was involved in the characterization of high-power and high-frequency transistors (DMOS and LDMOS). In 2002 he moved to STMicroelectronics in Catania (Italy) to support the RF products marketing group developing power amplifiers in order to evaluate and verify product performances in reference to customer specifications. Today he works as High Power Application Engineer supporting customers and exploring new applications for High Power MOSFETs devices.

Roberto Cammarata received a Master’s degree in Electrical Engineer from the University of Catania, Italy. He started out working in the earth satellite ground stations (Selenia_Marconi Comm.) microwave field in 1985. After that he went to work in Space Satellite Projects (Alenia Aerospace) and finally (Richardson and STM) in power amplifiers design for Communications and ISM RF applications.

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