Build data lanes into datacomms ASICs with Physical Coding Sublayer (PCS) IP core
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eeNews Europe
The JESD204B PCS IP Core performs frame generation, encoding, and scrambling for data transmission, as well as decoding, frame recovery, intra and inter lane alignment, and descrambling on data reception. It is highly configurable via an APB interface, and supports subclass 0, 1, & 2 data latency handling. For test purposes, the JESD204B PCS IP offers built-in PRBS generator/verifier pairs, as well as various loopback data path modes.
HDL Design House; www.hdl-dh.com
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