C-to-Silicon compiler used to speed video codec design
Renesas established its own coding style and reduced code size by almost half with SystemC to create the HEVC IP at a high level of abstraction. This enabled verification times that were six times faster than register-transfer level (RTL). This approach also enabled Renesas to use the C-to-Silicon Compiler to explore multiple algorithmic implementations to generate high-performance RTL while minimising power consumption and chip area. To eliminate any potential schedule impact from a significant engineering change order (ECO) late in the project, Renesas developed an ECO (engineering change order) flow using the C-to-Silicon Compiler with Encounter Conformal ECO Designer. This allowed them to use high-level synthesis to quickly apply and verify a patch to stay on schedule.
“The challenge with developing this HEVC/H.265-compliant IP was to incorporate our proprietary new algorithm, which enables high quality and high compression efficiently,” said Toyokazu Hori, department manager of Platform Base Technology Development Department, Automotive Information System Business Division at Renesas Electronics Corporation. “… we were able to implement the new algorithm very efficiently, achieving a good time-to-market for our advanced new IP.”
Cadence; www.cadence.com/news/ctosilicon
Renesas; www.renesas.com/press/news/2013a/news20131029.jsp
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
