Cadence accelerates SoC verification with expanded IP portfolio
Cadence Design Systems has made available 15 new Verification IP (VIP) products that enable engineers too quickly and effectively verify their SoC designs to meet the specifications for the latest standards protocols. The new Cadence® VIP offerings empower customers to confidently develop their next-generation industrial, automotive, hyperscale data center and mobile SoCs while keeping pace with the latest industry standards, including LPDDR5x, MIPI® CSI-2® 4.0 and UFS 4.0, and the newest versions of the USB4, Arm® AMBA® 5 CHI and GDDR interfaces.
The latest Cadence VIP offers customers a comprehensive verification solution for the most complex protocols. Cadence customers have access to a consistent API across all VIP with complete bus function models (BFMs), integrated protocol checks and coverage models, facilitating rapid adoption. The VIP supports multiple application areas and specifications.
These include Industrial: MIPI I3Csm 1.1, MIPI CSI-2 4.0, and eUSB2 1.2 — Automotive: MIPI A-PHYsm 1.0; MIPI DSI-2sm 2.0, Flash ONFI 5.0, and CAN XL — Hyperscale data center: CCIX 2.0, latest version of AMBA CHI; and the latest version of GDDR —Consumer and mobile: DisplayPort 2.1, Ethernet 5G, LPDDR5x, latest version of USB4, and UFS 4.0.
All Cadence VIP offerings include Cadence TripleCheck™ technology, which provides users with a specification-compliant verification plan linked to comprehensive coverage models and a test suite to ensure compliance with the interface specification. The new VIP also supports the expanded Cadence System-Level Verification IP (System VIP), which provides SoC-level test libraries, performance analysis, and data and cache coherency checkers.
“STMicroelectronics has successfully utilized a broad range of Cadence VIP, including Arm AMBA, Memory Models, MIPI I3C and CSI-2, eUSB2 and the advanced Cadence System VIP solution, which enabled us to deliver industry-leading products for key projects, including ST Industrial MCUs and MPUs,” said Philippe d’Audigier, system-on-chip hardware design director at STMicroelectronics. “Cadence continues to deliver new VIP offerings and advanced SoC verification technologies that support the latest standards.”
“As requirements evolve and demand increases for higher bandwidth, lower power and more effective cache coherency management, new protocols arrive to address these issues,” said Paul Cunningham, senior vice president and general manager of the System & Verification Group at Cadence. “By introducing these 15 new VIP offerings, Cadence provides customers with solutions that ensure they can keep up with evolving standards. Our customers can confirm their designs comply with the standard specifications and application-specific timing, power and performance metrics, providing the fastest path to IP and SoC verification closure.”
www.cadence.com/go/NewVerificationIP
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