Cadence acquires Altos Design Automation to extend advanced-node SoC design enablement
Shrinking process geometries increase process variations and make creation of accurate noise, power and timing models for foundation IP very complex given smaller time-to-market windows. Altos tools enable ultra-fast and accurate characterization of memory, standard cell libraries and other foundation IP, generating required models for SoC implementation. When combined with the Cadence end-to-end Silicon Realization portfolio, the offering gives customers greater visibility into the effects of noise, timing and power at every phase of the design cycle, including foundation IP design creation, extraction, SPICE simulation, and implementation.
“Foundation IP characterization is becoming mission critical at advanced nodes due to shrinking time-to-market windows, escalating low-power, high-speed design complexities, and variations in advanced processes,” said Dr. Chi-Ping Hsu, Senior Vice President, Research and Development, Silicon Realization Group at Cadence. “By extending our Silicon Realization tool offering to include technically superior solutions that automate vital phases of the design process, we deliver the end-to-end approach that is required to ensure our customers’ success.”
“Altos has established itself as the technology leader in foundation IP enablement, with a proven solution in use today by many of the world’s leading semiconductor and foundation IP providers,” said Jim McCanny, CEO and founder, Altos.
Altos has more than 30 customers, including 11 of the top 20 semiconductor companies.
Visit Cadence at www.cadence.com.
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