Cadence aims to recapture share of digital chip P&R with Innovus Implementation System
A Cadence spokesman openly acknowledges that in recent years, “We have been known for state-of-the-art in analogue and mixed-signal… we have not done so well in digital [chip design]” Innovus is the result of a long collaboration with foundries to produce an implementation package for next-generation technologies – but the company adds, “It’s not just for finFET; the benefits will be experienced with all geometries. One European early adopter has seen ‘dramatic’ improvements at 28 nm.”
Innovus is “Driven by a massively parallel architecture with breakthrough optimisation technologies,” – the company says that while the ability to use parallel compute resources comes from its revised approach, the speed-up is not only due to hosting on parallel compute resources; a large amount of the gain is also from the new algorithms involved.
The Innovus Implementation System was designed with several key capabilities to help physical design engineers target a set power/area budget or realise maximum power/area savings while optimising for a set target frequency. Cadence’s description of these upgrades lists;
– A new GigaPlace solver-based placement technology is slack driven and topology-/pin access/coloraware, enabling optimal pipeline placement, wire length, utilisation and PPA, and providing the best starting point for optimisation
– Advanced timing- and power-driven optimisation is multi-threaded and layer-aware, reducing dynamic and leakage power with optimal performance
– Concurrent clock and datapath optimisation includes automated hybrid H-tree generation, enhancing cross-corner variability and driving maximum performance with reduced power
– Next-generation slack-driven routing with track-aware timing optimisation that tackles signal integrity early on and improves post-route correlation
– Full-flow multi-objective technology enables concurrent electrical and physical optimisation to avoid local optima, resulting in the most globally optimal PPA
The Innovus Implementation System also offers multiple capabilities that boost turnaround time for each place and route iteration. Its core algorithms have multi-threading throughout the full flow, providing speed-up on industry-standard hardware with 8 to 16 CPUs. Innovus has a massively distributed parallel solution that enables the implementation of design blocks with 10 million instances or larger. Multi-scenario acceleration throughout the flow speeds runtime even with an increasing number of multi-mode, multi-corner scenarios.
SoC designs now have hundreds of blocks with millions of instances; handling large counts of instances allows more of a design to be flattened and run as a single entity, which usually leads to faster processing and smaller area.
Innovus offers a common user interface (UI) across synthesis, implementation and signoff tools, and data-model and API integration with the Tempus Timing Signoff solution and Quantus QRC Extraction solution. This constitutes, Cadence says, a “10nm-ready”, fast and accurate route to signoff closure.
Among customer endorsements from early uses is one from Freescale that is quotes as achieving a 7X gain in turnaround time over its previous production environment while maintaining its quality of results. The gains were achieved on multiple ~3M-instance 28-nm designs for networking applications, “We’ve tested the full Innovus Implementation System flow on some of our most congestion-challenged 28nm networking IP blocks and have achieved excellent results while seeing significant throughput improvements,” said Fares Bagh, vice president, hardware and architecture engineering in Freescale’s Digital Networking Group. “The new Cadence solution has enabled us to resolve our most difficult timing requirements, and we anticipate that our deployment will allow us to grow our IP block sizes and accelerate SoC-level design closure.”
Cadence; www.cadence.com/news/innovus
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