Cadence brings 16 nm FinFET chip IP into cars

Cadence brings 16 nm FinFET chip IP into cars

Technology News |
By Christoph Hammerschmidt

The IP portfolio includes key IPs for implementing the latest infotainment and ADAS systems-on-chips (SoCs) and includes Cadence’s flagship product, the LPDDR4/4X DDR PHY and controller suitable for clock rates up to 4266 MHz, and PCI Express 4.0/3.0 (PCIe4/3) PHY and controller. This offer is complemented by subsystems supporting MIPI D-PHY, USB3.1/USB2.0, DisplayPort, Octal SPI/QSPI, UFS and Gigabit Ethernet with Time Sensitive Network (TSN).

To enable cost-effective automotive SoC designs, the Cadence IP is optimized for surface area and performance in the temperature range according to AEC-Q100 Grade 2. This eliminates the need to make Grade 1 performance and space concessions in cost-sensitive automotive SoC designs. Cadence IP is ASIL-B-ready and suitable for ASIL-C/D, supporting the safety objectives and requirements of end users in accordance with the ISO 26262 standard.

Further information:

If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :    eeNews on Google News


Linked Articles