Cadence full-flow digital tool suite certified for GlobalFoundries’ 22FDX process
Through the certification process, the Cadence tools have been confirmed to meet all of GF’s accuracy criteria for its fully depleted silicon-on-insulator (FD-SOI) architecture, and customers using the Cadence digital tool suite on the GF 22FDX process technology can optimize power, performance and area (PPA) and reduce time-to-market.
To ease the design flow and process adoption, a number of Cadence tools support the new GF design flow, including a physical implementation tool, an RTL synthesis and physical synthesis engine, a complete timing analysis tool, a cell-level power integrity tool, a transistor-level power integrity solution with SPICE-level power signoff accuracy, a single, unified parasitic extraction tool that supports cell-level and transistor-level extractions during design implementation, a physical verification system, a signoff solution for design manufacturability and yield optimization, and a layout-dependent effect-aware re-simulation, layout analysis tool.
“Through our collaboration with Cadence, we’ve verified that the Cadence methodology meets our accuracy, frequency, power and cell utilization requirements,” said Richard Trihy, senior director, design enablement at GF. “The certification of the Cadence digital tool suite allows our mutual customers to reach their PPA targets and to experience the benefits associated with the GF 22FDX body bias techniques that are key differentiators with our process technology.”
Cadence – www.cadence.com
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