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Cadence gets EDA certification for TSMC 5nm and 7nm+ FinFET process technologies

Cadence gets EDA certification for TSMC 5nm and 7nm+ FinFET process technologies

Technology News |
By Christoph Hammerschmidt



Cadence’s digital, signoff and custom/analog tools now have the latest Design Rule Manual (DRM) and SPICE certification for the processes. The corresponding process design kits (PDKs) can now be downloaded. Customers using Cadence’s implementation, signoff and custom/analog tools are already in production with 7nm+ projects, and there are multiple design projects underway with early 5nm customers.

More information

https://www.cadence.com/go/tsmc5and7nmdandsoip

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