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Cadence has IP, tools for 16-nm FinFET Plus node

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By eeNews Europe

Currently under development for the 16 FF+ process, the Cadence IP portfolio includes multiple high-speed protocols for several key memory, storage and interconnect standards critical in the development of advanced SoC designs. Silicon-tested IP is expected to be available beginning in Q4 2014.

Cadence also announced the qualification of its digital implementation, signoff and custom/analogue design tools for the 16nm FinFET Plus process. Its digital and custom/analogue tools have achieved V0.9 Design Rule Manual (DRM) and SPICE certification from TSMC for its 16FF+ process: 16FF+ V1.0 certification is on track to be concluded by November 2014. Cadence also collaborated with TSMC to make several enhancements to its Custom Design Reference Flow (CDRF) for the 16FF+ process. Additionally, Cadence and TSMC are collaborating on the 10nm FinFET process, and Cadence says solutions are ready to support 10nm early customer design starts.

The Cadence custom/analogue and digital implementation and signoff tools have been validated by TSMC on high-performance reference designs in order to provide customers with the fastest path to design closure. Cadence tools certified for 16FF+ include Encounter Digital Implementation System, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Quantus QRC Extraction Solution, Virtuoso custom design platform, Spectre simulation platform, Physical Verification System, Litho Physical Analyzer and CMP Predictor.

Enhancements to the CDRF include an exclusive TSMC application programming interface (API) incorporated into Virtuoso Analog Design Environment GXL that speeds up statistical simulation flow, a new design methodology usung module generator (ModGen) technology for designing FinFET arrays to avoid density gradient effects, and the introduction of the electrically-aware design (EAD) platform to extract and analyse real-time parasitics and electromigration (EM) violations during design implementation. Cadence tools in the flow include Virtuoso custom design platform, Integrated Physical Verification System, Physical Verification System, Quantus QRC Extraction Solution, Spectre simulation platform, Voltus-Fi Custom Power Integrity Solution and Litho Electrical Analyser.


According to Dr. Chi-Ping Hsu, senior vice president, chief strategy officer, EDA and chief of staff to the CEO at Cadence, “Customers that create chips for the world’s newest mobile devices are already tapping into the benefits of the 16nm FinFET Plus design flows and can start to adopt 10nm FinFET solutions to overcome design complexity and get to market faster.”

“Our new 16nm FinFET Plus process is an important development for next-generation SoC designs as they balance the task of increasing performance while reducing power and area,” said Suk Lee, senior director of the Design Infrastructure Marketing Division at TSMC.

“Our broad portfolio of IP for 16 FinFET Plus will enable design teams to ramp quickly on next-generation SoC designs and immediately realize the performance and power benefits of this new FinFET process,” stated Martin Lund, senior vice president and general manager of the IP Group at Cadence.

Cadence; www.cadence.com


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