Cadence moves to a more software-centric approach to complex SoC verification
Perspec focuses on use-case scenarios; that is, a top-down rather than bottom-up approach to system verification in which the test are derived from the final, intended, functionality of the device. Part of what Perspec does centres on examining the range of possible tests that can be derived from the high-level functionality, and selecting those that give a high level of test coverage.
Perspec produces tests that can be used and re-used at a number of different stages of a complex system’s development, specifically at each level of abstraction at which the chip is depicted, prior to silicon implementation.
Claims for Perspec include that it reduces complex use-case scenario development effort for SoC verification from weeks to days; and that it improves SoC quality by accelerating the development of complex software-driven tests and integrated debug to reproduce, find and fix complex SoC-level bugs.
Perspec’s use-case scenario-based software-driven system-on-chip (SoC) verification is driven by a graphical specification of system-level verification scenarios and a definition of the SoC topology and actions; it can reduce complex test development from weeks to days, Cadence says, while also allowing design teams to reproduce, find and fix complex bugs to improve overall SoC quality.
Perspec System Verifier features include;
• A Unified Modeling Language (UML) based view of system-level actions and resources that, combined with solver technology, creates an intuitive view of complex and hard-to-test system-level use-case interactions
• The Solver technology, which automates the generation of portable tests to deliver complete coverage of system-level scenarios based on chip constraints and the scope of the scenarios to verify SoC-level features for functionality, performance and power
• Tests that run on all pre-silicon verification platforms including simulation, acceleration and emulation, and virtual and FPGA prototyping, which can be further used to validate actual silicon
“Today’s verification teams face a challenge in that the bottom-up approach to IP verification does not extend to the SoC level, and they are looking for an opportunity to move to top-down scenario-based verification in order to extend traditional approaches like UVM and achieve better coverage,” said Charlie Huang, executive vice president, Worldwide Field Operations and System & Verification Group at Cadence. “With its SoC-level constraint-solving technology, Perspec System Verifier is enabling our customers to create tests previously not feasible, increasing their confidence that they are meeting SoC functional requirements while speeding time to market.”
Cadence; www.cadence.com
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