Enabling up to four times the performance of conventional memory interfaces, the Cadence wide I/O interface not only meets the performance metrics of the proposed specification, but includes optimizations such as traffic reordering and several low-power features that lead to better overall system operation. Complemented by memory models, verification IP (VIP) and a sophisticated 3D IC design methodology, the wide I/O IP lowers the risk and overall cost of SoC design.
Wide I/O, a memory interface standard in review at JEDEC, defines a 512-bit wide interface to increase the bandwidth between memory and logic. The interface operates at a peak data transfer rate of 12.8 gigabytes per second (GB/s), which is up to four times the performance of conventional low-power memory solutions. The wide I/O interface allows a large array of low-cost and low-power connections between an application processor and the DRAM stacked on top of it. The result is a system that can achieve higher bandwidth with less power while also meeting the goals of reduced PCB area and component height. As a result, it is critical that designers also have access to advanced 3D IC assembly and design methodologies.
Designed to enable maximum system-level performance, the wide I/O memory controller includes advanced algorithms to ensure highly efficient data transfer and to intelligently schedule transactions, delivering unprecedented sustained and peak performance for mobile applications. The IP has the capability of reordering traffic by monitoring system transactions and delineating between low priority and system critical tasks. The capabilities enable the IP to maximize bandwidth and minimize latency on critical transactions.
The Cadence wide I/O interface also goes beyond the proposed low-power metrics of the standard, offering additional power-saving features such as “traffic sensing,” which automatically adjusts the power consumption based on the type of traffic. The IP has been designed to support operation at multiple frequencies, and allows designers to implement advanced power-control techniques, such as dynamic voltage and frequency scaling (DVFS), to reduce power even further. A flexible and configurable design allows the memory controller IP to be custom-fit for each SoC, further reducing time-to-market and risk.
Because the majority of wide I/O designs will require stacking of memory on top of logic, designers will need a sophisticated, comprehensive 3D IC platform for realizing their SoCs. The Cadence 3D IC platform includes advanced capabilities, such as support for through-silicon vias (TSVs), to enable the use of vertical electrical connections for significantly reduced board space, cost and power.
A 3D IC approach also requires expertise in all aspects of design, from digital and analog circuitry to packaging and PCB design layout. Offering digital, mixed-signal and analog end-to-end flows, as well as advanced PCB layout expertise, Cadence offers the holistic approach required to successfully integrate the wide I/O interface onto a SoC.
The Cadence wide I/O memory controller and supporting VIP are available now.
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