Cadence, Samsung accelerate 3nm mixed-signal silicon
Cadence Design Systems has worked with Samsung Foundry to boost the development of 3nm mixed signal chips.
The Mixed-Signal OpenAccess-ready process design kit (PDK) technology files support a range of Samsung process technologies from 28FDS down to GAA base 3nm. This means the qualified Cadence custom and digital design tools seamlessly interoperate on various Samsung process technologies for mixed-signal designs used in data centres, networking, 5G, mobile, industrial and automotive applications.
The PDK uses a common OpenAccess database and follows the announcement of the qualification of Cadence tools on 3nm last year and the taping out of a 3nm chip at Samsung Foundry. This co-design methodology promotes shared responsibilities and collaboration between the analog and digital teams for chip planning, design, implementation, physical verification, and signoff, improving overall productivity and increasing design throughput.
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The design flow supports advanced floorplanning and pin optimization so that users can pre-plan sensitive analog parts of the design using constraint-driven placement in the Virtuoso platform, then open the same design in the Innovus system for timing-driven placement of digital blocks. Users can fix pin locations or move them in either tool to optimize routing.
The block and chip routing capabilities means users can pre-route sensitive analog nets using custom design tools and finish the rest using a fast timing-driven router with in-design DFM hotspot detection and automated fixing to fulfil the mandatory DFM signoff requirements.
Improved static timing analysis (STA) automatically recognize logic cells on the timing path in mixed-signal design and perform timing analysis while ignoring analog circuitry that does not impacting timing while faster electromigration IR drop (EM-IR) analysis for mixed-signal designs is supported through a new hierarchical approach.
The digital tools in the PDK are the Innovus Implementation System, Genus Synthesis Solution, Liberate Characterization Suite, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Quantus Extraction Solution, Physical Verification System, Tempus Timing Signoff Solution, Voltus-Fi Custom Power Integrity Solution, and Litho Physical Analyzer. The custom tools included in the PDK are the Virtuoso ADE Product Suite, Virtuoso Schematic Editor, Virtuoso Layout Suite, Virtuoso Layout Suite Electrically Aware Design (EAD), Spectre X Simulator, and LDE Electrical Analyzer.
“We have qualified the Cadence Mixed-Signal OpenAccess-ready PDKs, and our IP designers are taking advantage of the interoperability of the Virtuoso and Innovus flow for our internal designs,” said Jongwook Kye, vice president, Foundry Design Enablement at Samsung Electronics. “This flow is available to our mutual customers immediately and will allow them to create high-quality designs on our various process technologies. This collaboration signifies further progress in our ongoing innovation with Cadence and ensures our customers continue to have access to the tools needed to improve productivity and speed their design process.”
“In collaboration with Samsung, we’ve developed a Mixed-Signal OpenAccess PDK that enables customers to create mixed-signal designs for emerging applications more effectively,” said Michael Jackson, corporate vice president, R&D in the Digital & Signoff Group at Cadence. “With this new PDK, customers can leverage the Cadence digital and custom tools and Samsung’s process technologies to achieve improved power, performance, and area and successfully deliver new designs within tight market windows.”
www.cadence.com/go/Samsung3nmMS.
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