Cadence, Samsung bring AI to SoC, 3D-IC and chiplet design
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Cadence and Samsung Foundry have expanded their collaboration with a new multi-year IP agreement and joint development of advanced AI-driven flows on the latest SF2P and other advanced process nodes. Specifically, the multi-year IP agreement will expand Cadence memory and interface IP in Samsung Foundry’s SF4X, SF5A and SF2P advanced process nodes.
By leveraging Cadence’s AI-driven design technology and Samsung’s advanced SF4X, SF4U, and SF2P process nodes, the collaboration aims to deliver high-performance, low-power solutions for AI data centres, automotive, ADAS and next-generation RF connectivity applications.
“We support a full portfolio of IP, subsystems and chiplets on the Samsung Foundry process nodes, and our latest multi-year IP agreement strengthens our ongoing collaboration,” said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence. “By combining Cadence’s AI-driven design and silicon with Samsung’s advanced processes, we’re delivering the leading-edge technologies our mutual customers need to innovate and bring their products to market faster.”
Hyung-Ock Kim, vice president and head of the Foundry Design Technology Team at Samsung Electronics, added, “Cadence’s suite of digital tools from RTL to GDS is now certified for Samsung’s latest SF2P process node, supporting advancements like Hyper Cell and LLE 2.0 technologies. Cadence and Samsung are also collaborating closely to enable analogue migration, enhance power integrity and improve thermal and warpage analyses for 3D-ICs using GPU acceleration. Additionally, a multi-year agreement between Cadence and Samsung Foundry to expand memory and interface IP solutions further strengthens our partnership.”
The new multi-year agreement will provide advanced memory and interface IP designed for AI, high-performance computing (HPC), and automotive applications. The expanded SF4X IP portfolio includes LPDDR6/5x-14.4G, GDDR7-36G, DDR5-9600, PCI Express (PCIe) 6.0/5.0/CXL 3.2, Universal Chiplet Interconnect Express (UCIe)-SP 32G, and 10G multi-protocol PHY (USB3.x, DP-TX, PCIe 3.0, and SGMII) with companion controller IP, enabling complete subsystem silicon. The LPDDR5X-8533 PHY IP, designed for automotive applications, completes the SF5A IP platform, while the introduction of a new 32G PCIe 5.0 PHY to the existing SF2P offering satisfies the requirements of leading AI/HPC customers.
Based on an extensive design and technology co-optimisation (DTCO) project, Cadence’s digital full flow has been certified for the latest Samsung SF2P process node, including the Samsung Hyper Cell methodology. Furthermore, Cadence has implemented support for Samsung Local Layout Effect (LLE) timing accuracy. Cadence and Samsung are also collaborating on DTCO for next-generation process nodes.
The Cadence Pegasus Verification System is certified for Samsung SF2P and additional Samsung nodes. The Cadence physical verification flow is optimised to enable mutual customers to achieve signoff accuracy and runtime goals with massive scalability, thereby enabling faster Time-to-Market (TTM).
To address the migration of analogue designs, Cadence and Samsung Foundry have successfully automated the transfer of analogue cell-based 4nm IP to the advanced 2nm process node, enabling quicker turnaround times while maintaining functional and design intent. This migration underscores the significance of technology scaling and IP reuse in minimising development time and costs, paving the way for future migrations of analogue cells and other IPs across various process nodes.
The two companies also successfully demonstrated a comprehensive Front-End Module (FEM)/Antenna-in-Package (AiP) co-design flow for next-generation mmWave applications based on Samsung’s 14nm FinFET process. The design turnaround time was accelerated by streamlining design data management across each stage of IC/module development, from initial system-level budgeting through RFIC/package co-design, analysis, and post-layout verification.
Cadence and Samsung have also collaborated on comprehensive full-flow power integrity analysis for 3D-ICs, spanning the entire process from early exploration to final signoff, utilising advanced Cadence EDA tools, including Voltus InsightAI, Innovus Implementation System, and the Integrity 3D-IC Platform. Applied to a high-speed CPU chip using Samsung’s SF2 node, Voltus InsightAI achieved an impressive 80-90% resolution of IR-drop violations with minimal impact on timing and power, showcasing its ability to balance power integrity with performance needs.
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