MENU

Big 3 EDA back ARM automotive chiplet push

Big 3 EDA back ARM automotive chiplet push

Business news |
By Nick Flaherty

Cette publication existe aussi en Français


Cadence, Siemens and Synopsys are aiming to boost the use of ARM’s automotive cores in chiplets and system on chip designs with a series of tools. However Synopsys is so far missing from the series of orchestrated announcements.

Synopsys is also a key supporter of ARM in automotive and a leading developer of chiplet design tools and IP. However it has its own competing IP cores based on the ARC and RISC-V architecture, and is currently pursuing a $35bn acquisition of simulation tool maker Ansys.

With ARM, the ADAS chiplet reference design and software development platform developed by Cadence aims to accelerate time-to-market for software defined vehicles (SDV) for its own AI accelerators.

“The automotive industry’s move to the software defined vehicle means that traditional software and hardware development processes are no longer valid and must evolve to meet the industry’s demands. Our partnership with ARM supporting accelerated simulation environment with Cortex-A720 AE CPU are helping to address automotive industry challenges by reducing time-to-market for SDV software through the availability of accelerated automotive platforms well ahead of silicon,” said Mike Ellow, Executive Vice President, Electronic Design Automation, Siemens Digital Industries Software.

The Cadence automotive reference design, initially for advanced driver assistance system (ADAS) applications, specifies a scalable chiplet architecture and interface interoperability with the UCIe protocol and IP

The software stack development platform is provided as a digital twin of the hardware that is compliant with the Scalable Open Architecture for Embedded Edge (SOAFEE) initiative software standard. This helps software development begin before hardware is available and allowing subsequent system integration validation.

Cadence sees chiplets and 3D-Ics as an increasingly popular architecture for automotive designs but these also need early software support.

 The architecture and reference design provide a standard for chiplet interface interoperability with the Helium Virtual and Hybrid Studio for the rapid creation of virtual and hybrid platforms and Helium Software Digital Twin to support deployment at scale for software developers

IP includes the Neo neural processing unit (NPU), the NeuroWeave software development kit (SDK) for machine learning (ML) solutions, and DSP from Tensilica.

 “The automotive industry is evolving rapidly and AI and software advancements are emphasizing a greater need to speed up development cycles,” said Dipti Vachani, senior vice president and general manager, Automotive Line of Business, ARM. “Together with critical ecosystem partners like Cadence, we’re enabling faster software and hardware development by bringing together a complete solution of design and verification technologies underpinned by the latest Automotive Enhanced technologies from Arm, allowing developers to start building for next-generation SDVs well before silicon is available in the market.”

 “Reducing the overall system design workload and shifting hardware and software development left are both crucial to meet shrinking time-to-market windows when developing today’s increasingly complex SDVs. Virtual platforms and chiplets are both key enablers for automotive 3D-IC SoC developers,” said Paul Cunningham, senior vice president and general manager of the System Verification Group at Cadence. 

“The increasing amount of electronics in cars and the transition to software-defined vehicles requires leveraging digital twins of the electronics to reshape the automotive development cycle and accelerate innovation. Synopsys’ long-standing collaboration with ARM and its ecosystem is providing automotive developers with leading solutions from early architecture exploration to rapid automotive software testing and system validation for designs powered by ARM’s latest automotive-enhanced processor IP,” said Tom De Schutter, Vice President of Engineering, Systems Design Group at Synopsys.

If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :    eeNews on Google News

Share:

Linked Articles
10s