Cadence tapes out DSP chip on 22nm using ABB Adaptive Body Bias

Cadence tapes out DSP chip on 22nm using ABB Adaptive Body Bias

Technology News |
By Nick Flaherty

Cadence Design Systems has taped out a test chip on the GlobalFoundries 22FDX platform using a new technique called Adaptive Body Bias (ABB).

The test chip uses the Tensilica HiFi 5 and Fusion F1 DSPs, which are aimed at designs for IoT, voice processing and always-on sensor fusion. The test chip produced the desired results, demonstrating ultra-low power and ultra-low voltage. FD-SOI allows the biasing of the transistor’s body that acts as a back gate, and the adaptive approach can compensate for process, voltage, and temperature (PVT) variations by controlling the threshold voltage. This boosts performance, lowers current leakage and improves yields.

“This tapeout validates the performance of the Cadence digital flow and Tensilica DSPs in conjunction with ABB enablement, which is a key differentiator for customers using our 22FDX platform,” said Mark Ireland, vice president of Ecosystem and Design Solutions at GF. “The Tensilica DSPs’ compelling PPA results with drain power voltage down to 0.5V are increasingly important to our customers designing portable devices that demand the extreme energy efficiency offered by our 22FDX solutions.”

GF’s 22FDX process is used for a range of applications, including single-chip radio frequency (RF) and mixed-signal SoCs, which is a logical fit for Tensilica IP. The Tensilica HiFi 5 DSP is used for artificial intelligence (AI) speech and audio processing in digital assistants, infotainment and other voice-controlled products. The Tensilica Fusion F1 DSP runs the narrowband communications standards typically associated with IoT communications, such as Bluetooth Low Energy, Thread and Zigbee, Wi-Fi and global navigation satellite systems (GNSS).

The test chips shows that ABB can be used with the Cadence digital full flow that incorporates unified implementation and timing- and IR-signoff engines, offering enhanced signoff convergence, reduced design margins and iterations, optimal power, performance and area (PPA) and improved throughput. This achieves convergence by concurrently closing the design for all physical, timing and reliability targets.

For designers who want to combine digital, RF, mixed-signal and custom designs on the same 22FDX chip, GF offers a Cadence-based mixed-signal OpenAccess process design kit (PDK) to improve productivity.

“Cadence’s ongoing collaboration with GF to provide premier solutions to our joint customers has resulted in this compelling full-flow tapeout proof point with extremely attractive Tensilica DSP power, performance and area metrics,” said Sanjive Agarwala, Corporate VP, R&D, IP Group at Cadence. “Customers building products in the high-growth audio, voice, sensor fusion and communications markets can benefit by achieving highly efficient energy results, very low voltages and reduced project times with our digital flow and Tensilica HiFi 5 and Fusion F1 DSPs on GF’s 22FDX platform.”

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