Cadence validates 12.8 Gbps Gen2 DDR5 MRDIMM IP system
Cadence has announced the first DDR5 12.8 Gbps MRDIMM Gen2 memory IP system on the TSMC N3 process, addressing the need for greater memory bandwidth for AI processing demands in enterprise and data centre applications, including AI in the cloud.
The new 12.8 Gbps DDR5 MRDIMM IP boasts a new high-performance, scalable and adaptable architecture based on Cadence’s proven and highly successful DDR5 and GDDR6 product lines.
The Gen2 DDR5 IP provides a PHY and a high-performance controller as a complete memory subsystem. The design is validated in hardware using the latest MRDIMMs (Gen2), achieving a best-in-class data rate of 12.8 Gbps that doubles the bandwidth of current DDR5 6400 Mbps DRAM parts. The DDR5 IP memory subsystem is built on Cadence’s silicon-proven, high-performance architecture, ultra-low latency encryption, and industry-leading RAS features. The DDR5 MRDIMM Gen2 IP is designed to support advanced SoCs and chiplets with flexible floorplan design options, while the new architecture enables fine-tuning of power and performance according to individual application requirements.
“The Cadence DDR5 IP portfolio, together with Micron’s industry-leading 1γ (1-gamma)-based DRAM, meets the increasing demand for higher memory bandwidth, density and reliability for AI processing workloads. These memory enhancements are pivotal in enabling the next generation AI/ML and HPC applications in data centre and enterprise environments,” said Praveen Vaidyanathan, vice president and general manager of Micron’s Data Center Products.
Data centre and enterprise applications stand to gain a significant performance advantage from Cadence’s DDR5 12.8 Gbps MRDIMM IP system, as evidenced by large customers turning to Cadence to deliver this innovative technology,” said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence. “This new leading-edge memory IP system raises the bar and establishes a roadmap that future-proofs our customers’ next-generation SoC and chiplet products for generations to come.”
The DDR5 controller and PHY have been verified with Cadence’s Verification IP (VIP) for DDR to provide rapid IP and SoC verification closure.
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