Caence/Tensilica shapes DSP IP for low-energy SoC implementations

Caence/Tensilica shapes DSP IP for low-energy SoC implementations

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By eeNews Europe

The current trend to a large upswing in sensors, sensor data collection and the associated need for data processing calls for a suitable DSP-capable resource, Cadence says; the Fusion digital signal processor (DSP) is based on the Xtensa Customizable Processor, and Cadence is aiming it at applications requiring merged controller plus DSP computation, ultra-low energy and a small footprint. It can be designed into systems on chip (SoCs) for wearable activity monitoring, indoor navigation, context-aware sensor fusion, secure local wireless connectivity, face trigger, voice trigger and voice recognition.

The IP comes with “pre-built” options for common requirements spanning communications standards; optional Instruction Set Architecture (ISA) extensions are included to accelerate multiple wireless protocols including Bluetooth Low Energy, Thread and Zigbee using IEEE 802.15.4, SmartGrid 802.15.4g, Wi-Fi 802.11n and 802.11ah, 2G and LTE Category 0 release 12 and 13, and global navigation satellite systems (GNSS).

As with other Xtensa IP, Tensilica provides an “IDE generator” ; if you add extensions to the basic IP, the software will genrate both the processor IP, and and optimised set of development tools to match.

As a reference for a typical low-power application, Cadence quotes a power diagnostic derived from the Sensory Truly Handsfree always-on algorithm; running that, it says, the Tensilica Fusion DSP sets a new ultra-low-power benchmark using 25% less energy compared to the current low-power Cadence Tensilica HiFi Mini DSP. The company says that, as an optimised DSP architecture, it retains a significant performance margin in DSP tasks over a microcontroller with DSP capabilities. The IP comes with RTOS support, from its introduction date; OS ports are to the core Xtensa architecture – which is essentially unchanged in this introduction – so OS ports are relatively simple.

The Tensilica Fusion DSP combines an enhanced 32-bit Xtensa control processor with base DSP features and flexible algorithm-specific acceleration for a fully programmable approach, supporting multiple existing and developing standards and customer algorithms. Many IoT applications are space- and energy-constrained, but still require advanced sensor processing, wireless communications and control. IoT device designers can configure just the options they need using the Xtensa Processor Generator to create an optimized Tensilica Fusion processor. Tensilica Fusion DSP configurable elements include:

– Tightly integrated floating point

– 1-4 MACs supporting real and complex operations

– AES-128 encryption

– Flexible memory architecture

– MAC and PHY algorithm acceleration

– Audio/voice compatibility with the Tensilica HiFi architecture

The company notes that applications such as voice processing/recognition can require considerable 16-bit computation – but that they can also demand always-on operation. For such reasons, the architecture can apply quad 16-bit MACs but can scale back the portions that are not needed, and reduce operating frequency, to reduce power. Instruction size has been reduced wher appropriate (from earlier Tensilica cores) to 48bit, to be the minimum required.

The Tensilica Fusion DSP combines flexible hardware choices with a library of DSP functions and more than 150 audio/voice/fusion applications from over 70 partners. It also shares the Tensilica partner ecosystem for other applications software, emulation and probes, silicon and services.


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