Call for participation on CORE-V Chassis SoC project
The project will attempt to run a CV64A 64-bit core along with a CV32E 32-bit coprocessor core. The CORE-V Chassis evaluation SoC will be based on the NXP iMX platform, and will also feature 3D and 2D GPUs, MIPI-DSI and CSI display and camera I/O, hardware security blocks, PCIe connectivity, a GigE MAC, USB 2.0 interfaces, support for (LP)DDR4, multiple SDIO interfaces, and a range of peripheral blocks.The 64-bit CV64A core will be based on the RV64GC RISC-V core IP developed as part of the PULP Platform at the University of ETH Zurich. The CV64A core can operate at frequencies of 1.5GHz. The CV32E coprocessor core is based on the RV32IMFCXpulp RISC-V core IP, also from the University of ETH Zurich.
When the CORE-V Chassis is completed, it will form the basis of further multi-core evaluation SoCs. The CORE-V Chassis announcement is an open call for industry participation in the project.
More information
www.openhwgroup.org
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