Call for Presentations for Elektor online conference on RISC‑V

News | January 15, 2026

By Alexander Neumann

On April 15, 2026, Elektor will hold an online conference focused on the RISC‑V standard instruction set architecture (ISA). Owing to its open, modular, and highly adaptable design, RISC‑V is gaining increasing significance in embedded systems and microcontroller applications. The organizers are inviting experts in the field to submit strong presentation proposals for consideration. The call for presentations remains open until January 16.

The Elektor event “RISC-V – Open Architecture for Embedded, AI, and Automotive” targets professionals such as embedded systems engineers, hardware design specialists, firmware and software developers, as well as automotive and mobility engineers. It is also intended for experts from the semiconductor industry, academic researchers, and students. The conference provides these audiences with expert insights, current trends, and practical experience reports.

Call for Presentations: What Are We Looking for?

Elektor is seeking presentations that are tailored to the event’s target audience and address topics such as the following:

RISC-V ISA and extensions: Overview of basic ISA (RV32I, RV64I) and optional extensions (M, A, F, vector, matrix, and security extensions)
User-defined instructions and domain-specific architectures (DSA): How companies can develop their own instruction sets for automotive, AI, or IoT
Trends in modular designs and their impact on performance and scalability
Open-source chip design and European semiconductor strategy: Role of RISC-V in initiatives such as Chips JU and the EU Chips Act
Firmware development for RISC-V: Use of C/C++ and Rust, debugging, virtual prototyping, and open-source RTOS (e.g., Zephyr, RT-Thread)
Software porting and optimization: strategies for migrating from ARM/x86 to RISC-V, including compiler intrinsics and memory models
Cybersecurity and security for automotive and IoT: hardware security features (e.g., CHERI extensions), secure boot, and functional safety according to ISO 26262
Software-defined vehicle and E/E architectures: Use of RISC-V in zonal and centralized vehicle architectures
Cyber Resilience Act and SBOM: Regulatory requirements and best practices for compliance
ADAS and autonomous systems: RISC-V-based solutions for real-time and safety-critical applications
Matrix and vector extensions for AI: Acceleration of neural networks and ML workloads on RISC-V
Open educational resources and FPGA prototyping: Practical approaches for teaching and research
The importance of open standards for Europe and global supply chains
Business cases and licensing models: How RISC-V is changing the cost structure and speed of innovation

The presentations are planned to run for 45 minutes each, followed by a 15‑minute Q&A session for accepted proposals. The finalized program is expected to be published in early February, after which tickets for the online conference will become available for purchase.

Editor’s Note: eeNews Europe is an Elektor International Media publication.