Chinese manufacturer Calterah Semiconductor has introduced two new mmWave radar SoC product families – Alps-Pro and Andes. They are the preferred choice for small radar modules with low power consumption and are suitable for new applications in the vehicle interior.
Alps-Pro targets the L2+ intelligent bicycle radar with the advantage of cost efficiency. Andes, on the other hand, is designed for 4D premium and imaging radar and contributes to Level 3+ autonomous driving.
Alps-Pro was developed based on Alps’ mmWave radar SoC platform, but is more powerful and robust. It is a 4T4R SoC with low power consumption and the smallest die size among comparable products on the market. A forward-looking radar based on Alp-Pro can have a maximum detection range of 240 m and offers an angular accuracy of ±0.1° and a resolution of 3°.
Compared to the existing Alps products, the Alps-Pro product offers significant advantages. Examples include a more precise phase shifter; higher channel-to-channel isolation; larger RF link budget. An integrated baseband accelerator (BBA) handles all radar signal processing. The previous single-core CPU was replaced by a dual-core CPU, and the memory size was doubled. The chip received a 100 Mbit/s Ethernet interface; as a result, the throughput could be increased 19-fold.
In addition, Alps-Pro’s various debugging functions, easier management of CPU resources and ASPICE compliance provide greater ease of use and shorten time-to-market.
4-core CPU delivers 2000 DMIPS
At the same time, the company introduced the Andes product family, the next generation of its mmWave radar. It consists of two 4T4R radar SoCs in 22nm technology to realise 4D premium and imaging radar functions. In the areas of computing power, RF design, cascade function, debugging and cyber security, this family occupies a top position in the competitive environment.
It includes a 4-core CPU with more than 2000 DMIPS; a DSP that operates at least 2 times faster than comparable products; and a proprietary RSP for fast radar signal processing.
For debugging, the Andes chips offer JTAG and Aurora interfaces; multiple data channels and analysis modules.
To improve cyber security, an adaptation of the “security island” design has been made. In addition, the chip is equipped with a hardware accelerator that supports all encryption algorithms.
With exceptional computing power, Andes supports high-throughput data processing and advanced algorithms. The flexible architecture can meet the requirements of different usage scenarios and waveforms. The convenient debugging functions greatly facilitate development, and the superior hardware security module can well meet the ever-growing demand for cyber security.