Can 3D ICs learn from MEMS manufacturing experience?

Can 3D ICs learn from MEMS manufacturing experience?

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By eeNews Europe

Debates on Grenoble’s Minatec campus were all about figuring out ways to slash manufacturing costs in what turns out to be quite a process-intensive approach to miniaturisation.

Stacking multiple dice together or connecting them via an interposer, the so-called more-than-Moore approach to higher performance devices relies heavily on Through Silicon Via (TSV) interconnects. These involves extra material deposition steps for the vias to be etched and filled (the hot topic of last year’s 3D TSV Summit), wafer handling and thinning and then exposing the TSVs through selective etching. A final Chemical Mechanical Planarisation (CMP) step will open up the isolated vias and prepare the wafer to receive micro-bumps on top of the TSVs, so that another prepared wafer can be stacked on top of it (full wafer-to-wafer stacking) or alternatively, marrying together only known-good dice.

“The choice between the reconstituted wafer approach (assembled of known-good dice only) and the full wafer-to-wafer approach will very much depend on the final die size and the associated costs of managing yield”, according one participant. Usually, the smaller the die and the higher the yield, the more cost-efficient it becomes to perform full wafer-to-wafer stacking, effectively skipping a few process steps.

All these processes and assembly steps come on top of the normal IC manufacture, hence the cost-benefits are not always clear, especially in the consumer market where users want a thinner tablet year-on-year but are not overly concerned about having “3D IC inside”: they simply want it cheaper, or to get more performance at the same price.

Among the keynote speakers, there were many IC manufacturers and process equipment vendors, all assembled to demonstrate their readiness for the next killer app, or rather, trying to convince device makers that all the industry would benefit from pushing 3D TSV technology straight into the mass market. Yet, the killer app that would really pull 3D TSVs globally was not clearly identified; perhaps integrated MEMS sensors in wearable electronics; or those taking part in tantalising IoT market projections, hinted Mark Stromberg, principal analyst at Gartner.

The debates started with MEMS, with fairly relaxed design rules and where TSVs are comparatively easy to integrate. Because MEMS sensors frequently need to physically interact with their environment, their packaging has a direct impact on performance: it must be specific to each MEMS application (hermetically vacuum sealed at die level, or with a damping gas, sometimes with a diaphragm or an opening, sometimes requiring an optical window). In this context, TSVs are an enabler explained Dr. Eric Mounier, co-founder of market research company Yole Developpement.

Currently, the packaging is often large even if the MEMS die is small, Mounier noted, and the MEMS packaging assembly, test and calibration accounts for nearly 35% to 60% of a MEMS module’s total cost.  In that case, TSVs can not only drive package standardisation to decrease overall costs, they enable compact arrays, for example by removing wire-bonds or taking connections to the back of the die. “If you need a well-controlled atmosphere with a round gasket between the MEMS active part and the cap, then TSVs provide back-side access and eliminate leakage issues”, said Stephane Renard, CTO and co-founder of Tronics. “TSVs can simplify the MEMS’ reliability and architecture for better protection” he added. 

“TSVs are not for everyone”, commented Ian Rutherford, MEMS product marketing & business line manager at X-Fab. “We need to have a toolbox ready, but it will not be make or break for all businesses. Not all TSV processes are cheap, so you need to have the right trade-off between TSV use and device-shrink”, Rutherford added. Rutherford also noted that biomedical applications could drive more TSVs in 3D IC packaging: with hermetically sealed CMOS devices used in implantable electronics, package biocompatibility is key.

“Often, people focus on the mechanical sensor structure, with a lot of processes inside the cap for the insulation, the hermeticity. But using TSVs, you can replace some of the processes; sometimes, overall manufacture is simplified and there will be some economy made”, Renard clarified.

As for testing the 3D IC MEMS devices, technology manager at STMicroelectronics, Marco Ferrera said that at present, TSVs are not adding complexity. “You just add series resistance to capacitors” he said.

Christophe Zinck, application engineering manager at ASE Group, an Outsourced Semiconductor Assembly and Test (OSAT) service provider, observed that packaging alone accounts for 20 to 60% of the MEMS/Sensor device BOM, but it is also a key part of the MEMS function and design as it can create additional value. “To reduce packaging costs, we need to manage the application specificity of MEMS collectively, at a wafer-level process instead of packaging individual dice”, Zinck explained, mentioning ASE’s new 3D WLP toolbox for standardised operations in complex MEMS architecture.

“What’s more, the standardisation allows for volume production, enabling second-sourcing and cost efficiency through technology sharing” concluded Zinck. it Since 2013, the company is in volume production for full wafer-level packaged MEMSs using TSVs for chip-to-wafer assembly.

The toolbox presented by ASE includes wafer-level capping, wafer-to-wafer or chip-to-wafer assembly, wafer moulding, TSVs, and wafer-level redistribution and balling. On its 2015 roadmap, the OSAT plans thin film MEMS capping, wafer-to-wafer metal bonding and sealing, WLCSP of any MEMS connected on top of any ASIC using TSVs, or on top of active interposers embedding on or several ASICs.

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