CAN-FD IP redesigned for FPGAs

CAN-FD IP redesigned for FPGAs
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Arasan Chip Systems has redesigned its second generation of CAN IP for the CAN 2.0 and CAN FD specifications in FPGA designs. The controllers have been rearchitected and upgraded to reduce power consumption and area, which make them suitable for FPGA applications in addition to Arasan’s primary ASIC IP market.
By Nick Flaherty

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Arasan Chip Systems has redesigned its second generation of CAN IP for the CAN 2.0 and CAN FD specifications in FPGA designs.

The controllers have been rearchitected and upgraded to reduce power consumption and area, which make them suitable for FPGA applications in addition to Arasan’s primary ASIC IP market.

The 2nd Gen CAN IP controller core performs serial communication for CAN2.0 and CAN FD specifications, supporting CAN 2.0A and CAN 2.0B protocols, TT-CAN, CAN-FD (ISO 11898-1.2015, plus earlier ISO, and Non-ISO Bosch specifications).

The core is fully programmable up to 1 Mbps for CAN 2.0 and multiple devices and is designed to increase reliability, faster error reporting, features advanced Error management unit, prevents data loss during transmission and prevents message collisions.

The configurable controller cores can be integrated with the host processor using standard AMBA AHB/AXI interfaces with programmable Interrupts, data and baud rates, acceptance filters & flexible buffering schemes for fine-tuning to the specific application.

Arasan’s CAN IP has passed compliance through multiple licensees and ASIL requirements.

www.arasan.com/products/can-fd/

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