Imec has developed a dynamic random-access memory (DRAM) cell architecture that eliminates the capacitor and so can be stacked in a 3D structure.
Classic DRAM designs beyond 32GByte struggle to scale as they get smaller, largely as a result of the capacitor. Instead, imec has shown a design with two low power indium-gallium-zinc-oxide thin-film transistors (IGZO-TFTs) and no storage capacitor. IGZO-TFTs are well known for very low off-current, and the parasitic capacitance of the read transistor serves as the storage element.
The 2T0C (2 transistor 0 capacitor) cell has a retention time longer than 400s, which further reduces the power consumption with a much longer refresh rate. This can be implemented on the back end of a CMOS process (BEOL) to put layers of dynamic memory on top of logic.
Imec has built the transistors with a 45nm gate length on 300mm wafers and described the archicture in a paper at the IEDM conference this week.
“Besides the long retention time, IGZO-TFT-based DRAM cells present a second major advantage over current DRAM technologies. Unlike silicon, IGZO-TFT transistors can be fabricated at relatively low temperatures and are thus compatible with BEOL processing,” said Gouri Sankar Kar, Program Director at imec.
“This allows us to move the periphery of the DRAM memory cell under the memory array, which significantly reduces the footprint of the memory die. In addition, the BEOL processing opens routes towards stacking individual DRAM cells, hence enabling 3D-DRAM architectures.”
The scaling of DRAM memory is a key element for cloud computing and AI, which are areas the European Commission has identified as key for the region, especially in the Covid-19 recovery. There have also been many different architectures proposed to eliminate the capacitor in DRAM.
“Our breakthrough solution will help tearing down the so-called memory wall, allowing DRAM memories to continue playing a crucial role in demanding applications such as cloud computing and artificial intelligence,” said Kar.
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