CEA-Leti develops 16nm self-aligned split-gate memory cell
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Split-gate flash memories are made of two transistors: an access transistor and a memory transistor with a charge-trapping layer (nitride, Si nanocrystals etc.). Split-gate architectures use a low-access voltage and minimize drain current during programming, which leads to a decrease of the programming power compared to standard one-transistor NOR memories, explains the research center. Because programming energy decreases when memory gate length decreases, ultra-scaling is particularly relevant for contactless applications.
The memory gate has been reduced down to 16nm thanks to a poly-Si spacer formed on the sidewall of the select transistor. This approach avoids costly lithography steps during fabrication and solves misalignment issues, which are responsible for a strong variation of the electrical performances, such as the memory window.
The main challenges of this self-aligned technology concern the precise control of the spacer memory gate shape and of the memory gate length. Spacer gate has to fulfil two difficult requirements: being as flat as possible in order to get a silicidation surface as large as possible while insuring a functional contact, and getting a steep edge in order to control the drain-junction doping.
TEM images of ultra-scaled self-aligned split-gate device, with a memory gate length of 16nm.
Visit CEA-Leti at www.leti.fr
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