CEA-Leti operates Qubits in super cool CMOS
The work whose results will be presented at IEDM 2016 is based on a device consisting of a two-gate, p-type transistor with an undoped channel, all built on a 300-mm CMOS fab line. The qubit device, explains the paper, is derived from silicon nanowire field-effect transistors and relies on confined hole spins. It consists of a 10nm-thick and 20 nm-wide undoped silicon channel with p-doped source and drain contact regions, and two 30nm-wide parallel top gates, side covered by insulating silicon nitride spacers.
At cryogenic temperatures (circa absolute zero ºK), hole Quantum Dots (QD) are created by charge accumulation below the gates and the double-gate layout enables the formation of two QDs in series, controlled by voltages applied to their respective gates. The first gate defines a quantum dot encoding a hole spin qubit, and the second one defines a quantum dot used for the qubit readout.
Unlike other qubit demonstrations so far, the present research uses regular (albeit cooled down) FDSOI field-effect transistors. The standard single-gate transistor layout is only modified in order to accommodate the second gate for the qubit readout.
Another key innovation, the researchers emphasized, is the use of a p-type transistor, meaning that the qubit is encoded by the spin of a hole and not the spin of an electron. This specificity makes the qubit electrically controllable with no additional device components required for qubit manipulation. Indeed, all electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate.
“Our one-qubit demonstrator brings CMOS technology closer to the emerging field of quantum spintronics,” said Silvano De Franceschi, Inac’s senior scientist and co-author of the paper.
While superconducting circuits are already providing basic “quantum processors” with several qubits (up to nine), spin qubits in silicon are at a much earlier stage of development. The immediate next steps will be demonstrating a few (n>2) coupled qubits, and developing a strategy for long-range coupling of qubits.
Leveraging the integration capabilities of CMOS technology will be a clear asset for large-scale qubit architectures, expects De Franceschi who is also contributing to the MOS-QUITO (MOS-based Quantum Information Technology) European collaborative project, developing cryogenic CMOS electronics for the future co-integration of silicon qubits and classical control hardware.
Visit CEA-Leti at www.leti.fr
Visit CEA-Inac at inac.cea.fr
Visit the University of Grenoble Alpes at www.univ-grenoble-alpes.fr
Visit the MOS-QUITO project at www.mos-quito.eu
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