CEA looks to photonic chiplet links for exascale computing
French research groups CEA-List and CEA-Leti have shown some of the technologies achieving exascale high-performance exascale computing (HPC).
The invited paper at the IEDM conference this week highlighted demonstrator technologies around 3D stacking and chiplets to improve performance. CEA-Leti is also working on short range, high speed photonic links between chiplets.
“Profound evolutions brought by high performance computing (HPC) applications are based on continuous and exponential increases in computing performances over the past decades,” says Denis Dutoit, a CEA-List scientist and lead author of the IEDM paper. “Supercomputers will soon achieve exascale-level computing performances mainly thanks to the introduction of innovative hardware technologies around the processors.”
The CEA technologies presented in the paper are powering demonstrators in the ExaNoDe and INTACT projects, which have developed integrated prototypes with technology building blocks to support the EU’s drive towards exascale computing.
The two institutes combined CEA-Leti’s expertise in silicon and 3D sequential integration with CEA-List’s many-core architectures, which are differentiated by their high level of scalability and power efficiency. They have demonstrated the benefit of new integration methods and processes following two main paths: finer 3D interconnect pitches, leading to improved bandwidth between compute chiplets, and assembly technologies that allow increasing heterogeneity in packaging, which improves peak performance.
3D integration for HPC processors is a key part of the European Processor Initiative (EPI). This is developing a roadmap for a new family of low-power European processors for extreme scale computing, high-performance Big Data and a range of emerging applications.
“These R&D successes open a path towards heterogeneous processors that will enable exascale-level supercomputers,” said Dutoit. “We demonstrated that co-optimization of advanced architectures with 3D integration technologies achieves the level of computing performance and bandwidth required for HPC.”
Smaller chips, or chiplets, stacked on an active interposer allow modularity and reusability at low development costs and CEA-List also is investigating using this for HPC architectures in the embedded world for compute-intensive accelerators. For edge applications requiring a high level of computation and memory, such as artificial intelligence (AI), chiplet-based partitioning will enable the creation of a broad range of solutions to meet the needs for embedded AI. Potential uses include autonomous driving, transport applications and industry 4.0.
Current work at CEA-Leti addresses die-to-wafer direct hybrid-bonding technology, which offers denser 3D interconnects with better electrical, mechanical and thermal parameters, and allows ultrahigh-bandwidth capabilities in heterogeneous systems.
The lab is also working on high-density through silicon vias (TSV) (pitch 1 to 4 µms) to create together with die-to-wafer hybrid bonding a complete dense 3D stack. For the longer term, CEA-Leti is also investigating innovative photonic-interposer technology as a 3D-based photonic chiplet approach to enable interconnection of tens of computing chiplets with the resulting chip-to-chip communication bandwidth, latency and energy. This follows the announcement of the first LED on CMOS by MIT in the US.
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