“The next step is high performance with optics such as PAM-4 and 200G and next-generation coherent optical communications across the data center,” said Pialis.
One way that will be introduced is at the chiplet level rather than at the board level. Anything that can be done to reduce distances and capacitances saves energy, an imperative in the data center. “If you’ve got a data center power budget for an AI operation of 20W then only 10W is doing the machine learning.” The rest is on moving data and results in and out of the data center, he said. “We need more bandwidth and we need at lower power,” said Pialis.
However, the adoption of chiplets will, in turn, impact the IP licensing sector, potentially introducing a new generation of bare-die chiplet vendors. How rapidly that will grow may depend on how quickly standardization of interfaces is introduced.
“I think the best way to give some color around that is to tell you that Alphawave IP has US$750 million order pipeline. I believe half the applications are chiplet-based opportunities,” said Pialis.
This is almost double the depth of order pipeline that Alphawave had in April 2021.
Pialis acknowledges that TSMC is a market leader in supporting chiplet-style manufacturing. “A majority of chiplets will be crafted by TSMC, which has well-developed, in-house 2D, 2.5D and 3D packaging. But so does Samsung, so does Intel,” he said.
But there are challenges. For now, some aspects of chiplet engineering tend to be proprietary. This serves to reserve the activity to elite, high-value applications it also makes things more expensive than they might otherwise be. How you put it all together including handling, assembly, testing and EDA is not complete, Pialis said.
The Universal Chiplet Interconnect Express (UCIe) standards organization has gained exception momentum and is starting to make progress but the scope of the chiplet endeavour is broad and standardization will take time, Pialis said (see UCIe chiplet standard created by industry leaders).
“From a packaging perspective, multiple decisions have to be made, architectural partitioning decisions have to be made,” Pialis pointed out. Also many of the applications are highly specific. “It’s hard to build a chiplet that can service multiple applications,” Pialis added. The development also produces a blurring of the once-familiar boundary between foundries and OSAT (outsourced semiconductor assembly and test) companies.
Changing topics, I asked whether Alphawave has yet followed through on its intention to create an R&D presence in Cambridge in the UK. This was mentioned by Alphawave prior to its London IPO in May 2021.
“We are expanding by acquiring engineering teams,” said Pialis. “We were 120 people at the time of the IPO. We are now over 600 people. We are adding teams worldwide.
We are in Ottawa, Canada; San Jose in Silicon Valley. We’ve got a London team and sites in India and Taiwan.”
Pialis said that while Cambridge and the UK more generally has an excellent pool of processor IP developers, he is not planning to simply open an office and hold a recruitment drive. “Microprocessor development does integrate with the custom silicon design work the company is involved in,” Pialis said. But any move is likely to be through the acquisition of a functioning and productive team.”
Could that be in machine learning one of the hottest of topics both in the data center and at the edge. “Alphawave is not going to get in machine learning any time soon. We’ve got enough on in the connectivity opportunity,” Pialis concluded.
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