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CEO interview: Cadence is about enablement, collaboration

Interviews |
By eeNews Europe


The demands placed on EDA companies can also be viewed as spanning from the atomic scale of transistors up to the global scale of the Internet of Things and satellite communications. It can’t get much broader than that but Tan reckons that no EDA company is doing a better job of meeting them than Cadence.

The company offers expertise at three identifiable levels; core EDA tools for IC design, design tool sets such as Allegro and OrCAD for PCBs and on to sub-system design with IP blocks. The ideal is to have the three levels merge as a continuum to allow design ideas to move from the "napkin" system down to the detailed layout of billions of transistors and back up to the working system with software running on hardware – faultlessly.

Cadence’s three strands of EDA enablement cover the IC, the board and boxes. Source: Cadence, IMEC Technology Forum.

In 2013 Tan said his company would be moving up to address system and software issues. This was said in an interview at that year’s Cadence Live Europe user conference, held in Munich, Germany (see Munich Calling: Cadence is Ready for software). A couple of years later at the IMEC Technology Forum held in Brussels, Belgium, eeNews Europe challenged the Cadence CEO that further movement towards system-level support is not that evident.

Tan’s response is that 40 percent of Cadence’s revenue came from systems companies in 2014. In that year Cadence took in $1.581 billion in revenue and a made a net profit of $159 million. And in March 2013 Cadence started to become a significant force as an IP core provider with the acquisition of data-plane processor company Tensilica Inc.

Next: Enable without competing


Tensilica provides configurable and extensible processors along with processors optimized for audio, baseband, imaging that come with the software to meet various standards and protocols. Although there is no proprietary operating system offering from Cadence it does support third-party operating systems such as ThreadX from Express Logic, uC/OS II from Micrium, Nucleus Plus from Mentor Graphics, and ROSES from Tata Elxsi. Many engineers prefer to work with an open-source operating system such as Linux.

Tan also points out that the Sigrity acquisition, which dates back to 2012, brought with it system-level power and thermal design analysis capability.

And in 2014 Cadence acquired Forte Design Systems, the vendor of Cynthesizer, a SystemC-based behavioural synthesis tool that enables design creation at the higher level of abstraction and nudging into partitioning decisions as to what functionality should be done in hardware and what in software.

Enable without competing

"There is a lot of open source software out there and we often deal with companies where software is their added value. For example, in medical or automotive this is very specialist software. We want to help with what’s called ‘bare metal’ software but we don’t want to get into applications. Meanwhile our IP business is growing rapidly."

Market researcher Gartner takes a different view. Gartner’s annual IP core ranking (see Semi IP licensing growth slows, vendor ranking stabilizes) lists Cadence IP core revenues in 2014 at $125.8 million, flat compared with 2013. Without commenting on Gartner’s information Tan said: "Our IP business was 11 percent of revenue in 2014."

The Cadence IP factory covers the three vital ingredients of digital systems, processors, memory, and I/O. Source: Cadence, IMEC Technology Forum.

That puts Cadence’s IP business revenue at about $175 million and supports the strong growth claim. It wouldn’t change Cadence’s fourth position ranking and the fact that EDA rival Synopsys has a larger IP business. Gartner reckons Synopsys IP business was worth $371.1 million in 2014."Our [IP core] booking is strong and we are conservative with how we recognize IP revenue," said Tan. "And on the processor side we have teamed up with ARM."

Next: ARM and Cadence: BFFs?


In March 2015, Cadence and ARM expanded their partnership with the signing of a multiyear IP agreement that grants access to each other’s IP portfolios. As such Cadence-ARM can together provide a comprehensive set of circuit blocks (see Cadence, ARM enter strategic partnership on IP). There are still some areas where Cadence could expand its IP business, Tan said. "We are looking at the various pieces but we mustn’t compete with a customer like ARM."

So following non-compete policy marks out a number of areas where Cadence is choosing not to take its business. "We have no intention of going into graphics," said Tan. But it is not clear that ARM feels any such inhibition to limit its IP provision. ARM already offers processors and graphics and the company recently moved into radio. It created its Cordio portfolio of Bluetooth radio IP based around its acquisition of two US companies Wicentric Inc. and Sunrise Micro Devices Inc. (see ARM seeks energy harvesting edge in IoT push). "You always have some overlap but in partnership, as long as you are open, these things can be worked around," said Tan.

Memory IP and going below 28nm

Memory and memory interfaces are part of Cadence’s IP, courtesy of the acquisition of Denali Software but that does not mean Cadence expects to do basic research in embedded non-volatile memory technologies, even though there is a technology gap to be filled at the 28nm logic node.

"The carbon nanotube memory looks interesting, but does it have mainstream foundry support?" asked Tan, referring to non-volatile memory technology being developed by Nantero Inc. (Woburn, Mass.). "If it became an industry standard we would support it."

Tan said that in terms of process miniaturization there is a clear divergence going on between Cadence customers that want to go down to 10nm and beyond and others that are content to work at 28nm or higher nodes.

"That’s why 28nm is going to be a long-lived node. And that’s because 16/14nm may not bring any cost benefits. The only reason to move down to these lower nodes is performance," said Tan. "Video and graphics push performance and so will move down; mixed-signal can stay with 28nm."

Next: Collaboration needed


Tan said he does have customers pushing for 16/14nm process and 10nm. "We are working on 10nm and 7nm. We need to be there." The wave of complexity that this will bring was one of the reasons that Cadence undertook a major rewrite of its IC tools to equip them for massive parallel processing. This means they are able to scale to meet the challenge of leading edge design with billions of transistors.

But collaborative design is also fundamental to getting working chips at reasonable yield at these advanced nodes, said Tan. Part of that is in terms of reducing cost by sharing engineering. Often that involves a four-source team drawn from the customer, the EDA vendor, the IP provider and the foundry.

Typically that might be the customer plus, ARM, Cadence and TSMC although other combinations of IP supplier and foundry are also possible and have to be supported. One implication is that not all possible combinations can be supported. In fact at the leading edge developers are facing a few silicon-proven design collaboration choices.

Automotive on the move

One result of the changing landscape is that automotive IC design is moving faster than previously expected, said Tan. The domain is generally thought of as being mainly mixed-signal and power ICs and conservative because of the need to meet robustness and reliability issues. But it is now moving down through the logic nodes faster than before to reach 40nm, where embedded non-volatile memory is available, and to 28nm and even on to 16nm FinFET designs, Cadence says.

This is partly because of the increasing infotainment content in the relatively benign cabin environment of the automobile, but particularly because of the phase of rapid design for ADAS (automotive driver assistance systems) that is now going on. These ADAS designs are dominated by video and graphical information flows and require high-performance processing to make decisions rapidly, said Tan.

Next`: Whither FDSOI?


Whither FDSOI?

Does fully-depleted silicon on insulator (FDSOI), an alternative manufacturing style to the FinFET that uses simpler manufacturing on SOI wafers, have a place to play in the chip making universe? FDSOI has not been embraced by two of the largest chip manufacturers Intel and TSMC, although Samsung has agreed to be volume manufacturer for developer of the FDSOI process STMicroelectronics.

"There is some merit to FDSOI in terms of power. At 28nm/20nm some customers are using FDSOI for some special circuits. It is also being looked at for RF," said Tan. "We have worked with STMicroelectronics and the tools are ready," said Tan. "We follow where the customer goes," Tan said.

The message from Lip-Bu Tan is that while a move up to the system level may not be completely apparent, it is happening. "We call it system design enablement," said Tan. At the same time the company’s expertise is spanning an ever-broader range of complexity from nanoscale physics to advanced communications protocols and to do so must engage in even higher levels of collaboration.

Related links and articles:

www.cadence.com

News articles:

Munich Calling: Cadence is Ready for software

Semi IP licensing growth slows, vendor ranking stabilizes

Cadence, ARM enter strategic partnership on IP

ARM seeks energy harvesting edge in IoT push


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