CEO Interview: Calista Redmond of RISC-V International at Embedded World 2023
Calista Redmond, CEO of RISC-V International talks to Nick Flaherty at Embedded World (EW2023) about the open instruction set architecture breaking out of embedded.
“We are at maturity point and at a point in the technical development where there is a larger drive to compatibility,” she said. “First we are ratifying common profiles and in the process of setting up compliance and compatibility work – we are in early stages of that with ongoing resources provided by members.”
“This year we are seeing a lot more depth by industry, more uptake in automotive, datacentre for primary processing or adding AI accelerators and the work with Android is really starting to take off,” she said.
The cloud, AI and government drives for sovereign technology supply chains are all driving the growth, she says.
“We grew 30% last year to 3300 members, evenly distributed 30/30/30 between the US, Europe and Asia, from student engineers to the largest multinationals. We continue to see more investment, in the tens of billions, and its evident to us that companies are going deeper on RISC-V and this is coming to production. We saw $2bn in VC funding, with tens of billions in governments, the EU and India in particular. What governments are realising is the value in investing locally to help their technical environment but engaging globally.”
- Tackling the challenges of RISC-V
- Europe steps up as RISC-V ships 10bn cores
- Android Open Source Project ports to RISC-V
She points to a recent announcement by Qualcomm, which has been a key ARM partner, which has it has shipped 650m RISC-V cores embedded in its designs. This highlights the drive is to ease the compatibility. “Running multiple architectures makes business sense and we want to make the portability and migratory opportunity real for the entire ecosystem to move between RISC-V and others.”
“We’ve already had our first RISC-V compatible designation from Alibaba and there’s a lot of vertical development going on already with the developer ports, that’s a big focus for this year,” she said,
“We are seeing a huge increase in activity,” she said. “In Europe we see a lot more concentrated activity through EU research projects and we watch that from an HPC angle and that then tips in the commercial adoption.”
That will be one of the key themes for the first RISC-V Summit to be held in Europe, happening in June.
Virtual hardware
Another area is the development of virtual platforms to speed up software development.
“There are virtual platforms, Andes has a collaboration, and many others are doing things in this vein,” she said. These will be included in the RISC-C Exchange which hosts the hardware, software, services, and learning offerings in the RISC-V community.
“It’s our goal to run as easily on RISC-V as any architecture and optimise, to take advantage of vector extensions or different custom implementations,” she said.
Hyperscaler chips
- SiFive aims for ARM with high performance RISC-V vector cores
- Codasip, SiliconArts team on RISC-V ray tracing graphics IP
- Codasip, IAR show dual-core lockstep for RISC-V safety designs
“On the hyperscaler side we do see a lot more activity for that group. Alibaba recently had its cloud conference and we have a lot more going on with Tencent. We are seeing general purpose datacentre applications coming through. You’ve got Ventana and Tenstorrent embarking on high performance implementations with more announcements towards the Summit in November.”
“You watch how generations of technology have evolved in the datacentre,” she points out. “Interconnect used to be proprietary, but now the world has gone to Ethernet and that is now the prolific standard for datacentres. So making a RISC-V decision is the same as the global platform to build on.”
